Overview

⏵ Requirements: SPI_1

The following SPI commands are supported:

·       Local Register Read - LCL_REG_RD

·       Local Register Write - LCL_REG_WR

·       Global Register Write - GBL_REG_WR

·       Local LUT Read - LCL_LUT_RD

·       Local LUT Write - LCL_LUT_WR

·       Global LUT Write - GBL_LUT_WR

·       Local Fast Beam Steering - LCL_FBS

·       Global Fast Beam Steering - GBL_FBS

Local Register Read - LCL_REG_RD

⏵ Requirements: SPI_78, SPI_74, SPI_3

Local Register Read (LCL_REG_RD) is a 32-bit (4 bytes) SPI command bounded by the chip select (spi_csb) signal that reads the registers of the device. When there is a LCL_REG_RD command to a buffered registers, the content of the active register is read.

⏵ Requirements: SPI_80, SPI_4

The Chip Address given in byte1 selects the device to be accessed. If the Chip Address does not match the (pre-configured) chip address, the access will be ignored.

⏵ Requirements: SPI_5

Continuous read access and address roll-back is supported. Sending another 16 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command increases the register address, and data are transmitted accordingly. When reaching the register address 0xFF, the next access targets address 0x0.

⏵ Requirements: SPI_4, SPI_78, SPI_79, SPI_80, SPI_81, SPI_5

The following tables show the LCL_REG_RD frame structure.

Notes:

·       Chip Address:

Although F641x supports only 4-bit physical address, the digital block supports 5-bit chip address. The top bit is hard coded to 0 on-chip. This design also supports programming the chip-address using shift register blocks, where the chip can be assigned a 5-bit address.

·       Auto Burst Mode:

The Local Register Read SPI command provides auto burst mode. Sending another n times (n=1, 2, 3...) 16 clocks with the chip select signal asserted after the initial command fetches the next registers content. After register address 0xFF, data from register address 0x0 is sent. In auto burst mode, the command length becomes 4 + n*2 bytes.

·       Register Read Data:

When there is an access to a buffered register, the content of the active register is read.

Use cases:

1.       Read register contents from chip address 0x5 and register address 0x2A.

a.   SPI command: 0x05_2A_**_**

b.   Comment: During the last two bytes, the data will be sent on the SDO (MISO) line by the chip.

2.       Reading registers 0x40-0x43 from chip address 0xA.

a.   SPI command: 0x0A_40_**_**_**_**_**_**_**_**

b.   Comment: Registers 0x40, 0x41, 0x42, and 0x43 are read in sequence.

Local Register Write - LCL_REG_WR

⏵ Requirements: SPI_83

Local Register Write (LCL_REG_WR) is basically a 40-bit (5 bytes) SPI command bounded by the chip select (spi_csb) signal that writes data to registers of the device. When there is a LCL_REG_WR command to a buffered registers, it depends on the RF Load settings in byte3 if the content of the active register is updated, too.

⏵ Requirements: SPI_80, SPI_4

The Chip Address given in byte1 selects the device to be accessed. If the Chip Address does not match the (pre-configured) chip address, the access will be ignored.

⏵ Requirements: SPI_8, SPI_9, SPI_10, SPI_65

When the TX RF Load (TRL) bit in byte3 is set to 1, data of the TXVn and TXHn Set (TXVn/TXHn_SET, n = 1..4) buffer registers are transferred to the TXVn_SET and TXHn_SET active registers respectively. When the RX RF Load (RRL) bit is set to 1, data of the RXVn and RXHn Set (RXVn/RXHn_SET, n = 1..4) buffer registers are transferred to the RXVn_SET and RXHn_SET active registers respectively. A data transfer from the buffer to the active registers is initiated even if the chip address given in byte1 does not match the (pre-configured) chip address. When none of the RF Load bits are set to 1, then no data transfer from buffer to active registers occurs. Note that this behavior is independent of the CTRL_CFG[0] (TRX_CONT_MODE) setting.

⏵ Requirements: SPI_67, REG_95

When the TX DAC Load (TAL) bit in byte3 is set to 1, all DACs configured as 'PA' in the PA_LNA_DAC_CFG1 register are set according to DAC_ONn (n = 1..10) register values if all of the following conditions are met:

·       the DACs are enabled in the PA_LNA_DAC_CFG3 register.

·       Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high.

·       CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (SPI control).

·       the operating mode is set to 'TX'.

·       CTRL_CFG[6] (TAL_RAL_EN) is set to 1.

Setting the TAL bit to 0 switches all PA DACs to the PA DAC OFF state, meaning that the outputs are set according to PA_DAC_OFF register value.

⏵ Requirements: SPI_68, REG_95

When the RX DAC Load (RAL) bit in byte3 is set to 1, all DACs configured as 'LNA' in the PA_LNA_DAC_CFG1 register are set according to DAC_ONn (n = 1..10) register values if all of the following conditions are met:

·       the DACs are enabled in the PA_LNA_DAC_CFG3 register.

·       Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high.

·       CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (SPI control).

·       the operating mode is set to 'RX'.

·       CTRL_CFG[6] (TAL_RAL_EN) is set to 1.

Setting the RAL bit to 0 switches all LNA DACs to the LNA DAC OFF state, meaning that the outputs are set according to LNA_DAC_OFF register value.

⏵ Requirements: SPI_84, REG_99

Enabling and disabling of DACs is done even if the chip address given in byte1 does not match the (pre-configured) chip address. DAC_STATUS[13:12] ({ TAL, RAL }) bits hold the status of the DAC Load bits set in the last command.

⏵ Requirements: SPI_62

Data shall be committed in halfwords as the sixteen data bit of a data field. If the write access is not an even multiple of 16 clocks, the trailing data bits are not committed. There is an exception when { PSS, GAS } = 2b'10 or { PSS, GAS } = 2b'10 in byte3. In this case data shall be committed in bytes as the eight data bit of a data field. If the write access is not an even multiple of 8 clocks, the trailing data bits are not committed.

⏵ Requirements: SPI_11

When both Phase and Gain Set bits are set to 0 ({ PSS, GAS } = 2b'00) in byte3, then 16-bit data shall be provided in byte4 and byte5 as well as in all subsequent halfwords (if any). With this configuration (setting) it is expected that data are written to registers other than TXVn/TXHn/RXVn/RXHn_SET (n = 1..4). When writing to TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET registers with this setting, proper device operation is not guaranteed anymore.

⏵ Requirements: SPI_12, SPI_13

When Phase Set bit is set to 1 and Gain Set bit is set to 0 ({ PSS, GAS } = 2b'10), then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers shall be addressed and 8-bit data shall be provided in byte4 and all subsequent bytes (if any) corresponding to TX_PHASE_CTRL and RX_PHASE_CTRL bit fields respectively. When Phase Set bit is set to 0 and Gain Set bit is set to 1 ({ PSS, GAS } = 2b'01), then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers shall be addressed and 8-bit data shall be provided in byte4 and all subsequent bytes (if any) corresponding to TX_GAIN_CTRL and RX_GAIN_CTRL bit fields respectively. When writing to a register other then then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) with any of these settings, proper device operation is not guaranteed anymore.

⏵ Requirements: SPI_75

When both Phase and Gain Set bits are set to 1 ({ PSS, GAS } = 2b'11), then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers shall be addressed and 16-bit data shall be provided in byte4 and byte5 as well as in all subsequent halfwords (if any).

⏵ Requirements: SPI_104, SPI_105

When the Cyclic Redundancy Check (CRC) error detection feature is enabled - refer to section Cyclic Redundancy Check for more information - { NB1, NB0 } define the number of write data bytes that are transmitted. When CRC is disabled these bits are ignored.

⏵ Requirements: SPI_5

Continuous read access and address roll-back is supported. Sending another 16 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command increases the register address, and data are received accordingly. When reaching the register address 0xFF, the next access targets address 0x0.

⏵ Requirements: SPI_83, SPI_82, SPI_80, SPI_81, SPI_4, SPI_8, SPI_9, SPI_10, SPI_65, SPI_67, SPI_68, SPI_62, SPI_11, SPI_14, SPI_12, SPI_13, SPI_75, SPI_104

The following tables show the LCL_REG_WR frame structures.

Option 1: When { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11.

Option 2: When { PSS, GAS } = 2b'01 or { PSS, GAS } = 2b'10.

Option 1: When { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11.

Option 2: When { PSS, GAS } = 2b'01 or { PSS, GAS } = 2b'10.

Notes:

·       Bytes: n = 0, 1, 2, 3 …

·       Chip Address:

Although F641x supports only 4-bit physical address, the digital block supports 5-bit chip address. The top bit is hard coded to 0 on-chip. This design also supports programming the chip-address using shift register blocks, where the chip can be assigned a 5-bit address.

⏵ Requirements: SPI_5

·       Auto Burst Mode:

The Local Register Write SPI command provides auto burst mode. Sending another n times (n=1, 2, 3...) 16 (when { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11) or 8 (when { PSS, GAS } = 2b'01 or { PSS, GAS } = 2b'10) clocks with the chip select signal asserted after the initial command writes data to the next registers. After register address 0xFF, data from register address 0x0 are written. In auto burst mode, the command length becomes 4 + n*2 bytes.

⏵ Requirements: SPI_74

·       Register Write Data:

When there is an access to a buffered register, it depends on the RF Load settings if the data is written to the active register, too.

Use cases:

1.       Write 0x1234 to register 0x06 for chip 0x1A.

a.   SPI command: 0x3A_06_00_1234

b.   Comment: As this register is not buffered, it is updated even without setting any RF Load bit in the SPI command.

Global Register Write - GBL_REG_WR

⏵ Requirements: SPI_83

Global Register Write (GBL_REG_WR) is basically a 40-bit (5 bytes) SPI command bounded by the chip select (spi_csb) signal that writes data to registers of the device. When there is a GBL_REG_WR command to a buffered registers, it depends on the RF Load settings in byte3 if the content of the active register is updated, too.

⏵ Requirements: SPI_6, SPI_86

When the Sub-array Enable (SE) bit in byte1 is set to 1, the command is only executed when the Sub-array Index given in the same byte matches the Sub-array Index (SA_INDEX) of the device in the CHIP_INFO register. When SE is set to 0, the command is executed for all devices.

⏵ Requirements: SPI_8, SPI_9, SPI_10, SPI_65

When the TX RF Load (TRL) bit in byte3 is set to 1, data of the TXVn and TXHn Set (TXVn/TXHn_SET, n = 1..4) buffer registers are transferred to the TXVn_SET and TXHn_SET active registers respectively. When the RX RF Load (RRL) bit is set to 1, data of the RXVn and RXHn Set (RXVn/RXHn_SET, n = 1..4) buffer registers are transferred to the RXVn_SET and RXHn_SET active registers respectively. A data transfer from the buffer to the active registers is initiated even if the Sub-array Index given in byte1 does not match the Sub-array Index (SA_INDEX) of the device in the CHIP_INFO register. When none of the RF Load bits are set to 1, then no data transfer from buffer to active registers occurs. Note that this behavior is independent of the CTRL_CFG[0] (TRX_CONT_MODE) setting.

⏵ Requirements: SPI_67, REG_95

When the TX DAC Load (TAL) bit in byte3 is set to 1, all DACs configured as 'PA' in the PA_LNA_DAC_CFG1 register are set according to DAC_ONn (n = 1..10) register values if all of the following conditions are met:

·       the DACs are enabled in the PA_LNA_DAC_CFG3 register.

·       Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high.

·       CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (SPI control).

·       the operating mode is set to 'TX'.

·       CTRL_CFG[6] (TAL_RAL_EN) is set to 1.

Setting the TAL bit to 0 switches all PA DACs to the PA DAC OFF state, meaning that the outputs are set according to PA_DAC_OFF register value.

⏵ Requirements: SPI_68, REG_95

When the RX DAC Load (RAL) bit in byte3 is set to 1, all DACs configured as 'LNA' in the PA_LNA_DAC_CFG1 register are set according to DAC_ONn (n = 1..10) register values if all of the following conditions are met:

·       the DACs are enabled in the PA_LNA_DAC_CFG3 register.

·       Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high.

·       CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (SPI control).

·       the operating mode is set to 'RX'.

·       CTRL_CFG[6] (TAL_RAL_EN) is set to 1.

Setting the RAL bit to 0 switches all LNA DACs to the LNA DAC OFF state, meaning that the outputs are set according to LNA_DAC_OFF register value.

⏵ Requirements: SPI_84, REG_99

Enabling and disabling of DACs is done even if the Sub-array Index given in byte1 does not match the Sub-array Index (SA_INDEX) of the device in the CHIP_INFO register. DAC_STATUS[13:12] ({ TAL, RAL }) bits hold the status of the DAC Load bits set in the last command.

⏵ Requirements: SPI_62

Data shall be committed in halfwords as the sixteen data bit of a data field. If the write access is not an even multiple of 16 clocks, the trailing data bits are not committed. There is an exception when { PSS, GAS } = 2b'10 or { PSS, GAS } = 2b'10 in byte3. In this case data shall be committed in bytes as the eight data bit of a data field. If the write access is not an even multiple of 8 clocks, the trailing data bits are not committed.

⏵ Requirements: SPI_11

When both Phase and Gain Set bits are set to 0 ({ PSS, GAS } = 2b'00) in byte3, then 16-bit data shall be provided in byte4 and byte5 as well as in all subsequent halfwords (if any). With this configuration (setting) it is expected that data are written to registers other than TXVn/TXHn/RXVn/RXHn_SET (n = 1..4). When writing to TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET registers with this setting, proper device operation is not guaranteed anymore.

⏵ Requirements: SPI_12, SPI_13

When Phase Set bit is set to 1 and Gain Set bit is set to 0 ({ PSS, GAS } = 2b'10), then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers shall be addressed and 8-bit data shall be provided in byte4 and all subsequent bytes (if any) corresponding to TX_PHASE_CTRL and RX_PHASE_CTRL bit fields respectively. When Phase Set bit is set to 0 and Gain Set bit is set to 1 ({ PSS, GAS } = 2b'01), then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers shall be addressed and 8-bit data shall be provided in byte4 and all subsequent bytes (if any) corresponding to TX_GAIN_CTRL and RX_GAIN_CTRL bit fields respectively. When writing to a register other then then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) with any of these settings, proper device operation is not guaranteed anymore.

⏵ Requirements: SPI_75

When both Phase and Gain Set bits are set to 1 ({ PSS, GAS } = 2b'11), then TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers shall be addressed and 16-bit data shall be provided in byte4 and byte5 as well as in all subsequent halfwords (if any).

⏵ Requirements: SPI_104, SPI_105

When the Cyclic Redundancy Check (CRC) error detection feature is enabled - refer to section Cyclic Redundancy Check for more information - { NB1, NB0 } define the number of write data bytes that are transmitted. When CRC is disabled these bits are ignored.

⏵ Requirements: SPI_5

Continuous read access and address roll-back is supported. Sending another 16 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command increases the register address, and data are received accordingly. When reaching the register address 0xFF, the next access targets address 0x0.

⏵ Requirements: SPI_83, SPI_85, SPI_80, SPI_6, SPI_86, SPI_8, SPI_9, SPI_10, SPI_65, SPI_67, SPI_68, SPI_62, SPI_11, SPI_14,SPI_12, SPI_13, SPI_75, SPI_104

The following tables show the GBL_REG_WR frame structures.

Option 1: When { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11.

Option 2: When { PSS, GAS } = 2b'01 or { PSS, GAS } = 2b'10.

Option 1: When { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11.

Option 2: When { PSS, GAS } = 2b'01 or { PSS, GAS } = 2b'10.

Notes:

·       Bytes: n = 0, 1, 2, 3 …

⏵ Requirements: SPI_5

·       Auto Burst Mode:

The Global Register Write SPI command provides auto burst mode. Sending another n times (n=1, 2, 3...) 16 (when { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11) or 8 (when { PSS, GAS } = 2b'01 or { PSS, GAS } = 2b'10) clocks with the chip select signal asserted after the initial command writes data to the next registers. After register address 0xFF, data from register address 0x0 are written. In auto burst mode, the command length becomes 4 + n*2 bytes.

⏵ Requirements: SPI_74

·       Register Write Data:

When there is an access to a buffered register, it depends on the RF Load settings if the data is written to the active register, too.

Use cases:

1.       Write 0x1234 to register 0x06 for chip with sub-array index 0xA.

a.   SPI command: 0xAA_06_00_1234

b.   Comment: As this register is not buffered, it is updated even without setting any RF Load bit in the SPI command.

Local LUT Read - LCL_LUT_RD

⏵ Requirements: SPI_87

Local LUT Read (LCL_LUT_RD) is a 40-bit (5 bytes) SPI command bounded by the chip select (spi_csb) signal that reads data from the look-up tables (LUTs) of the device.

⏵ Requirements: SPI_80, SPI_4

The Chip Address given in byte1 selects the device to be accessed. If the Chip Address does not match the (pre-configured) chip address, the access will be ignored.

⏵ Requirements: SPI_66, SPI_15, SPI_16

There is a LUT with 128 entries at 64-bit per direction (TX/RX) and polarization (H/V) including four (4) channels at 16-bit per entry. When any of the LUT Pointer (TXV, TXH, RXV or RXH) bit in byte2 is set to 1, access to the associated LUT is enabled. Each LUT location information is completely read with 64 clock pulses (16 bits x 4 channels). When more than one LUT Pointer bit is set to 1, the LUTs are accessed in the following order: TXV -> TXH -> RXV -> RXH.

In general, a complete 64-bit LUT entry including all 4 channels is read with a single read access, starting with channel #1 and followed by channel #2 to #4. In this case the channel select bits ({ CH1, CH0 }) in byte2 must be set to 2'b00. However, if data of a particular channel of a single entry shall only be read, the channel select bits can be set according to the required channel number.

⏵ Requirements: SPI_89, SPI_17

The LUT Address given in byte3 provides the 7-bit address of the LUT to access. Continuous read access and address roll-back is supported. Sending another 64 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command increases the LUT address, and data are transmitted accordingly. When reaching the LUT address 0x7F, the next access targets address 0x0.

⏵ Requirements: SPI_87, SPI_88, SPI_4, SPI_80, SPI_15, SPI_89, SPI_87

The following tables show the LCL_LUT_RD frame structure.

Notes:

·       Chip Address:

Although F641x supports only 4-bit physical address, the digital block supports 5-bit chip address. The top bit is hard coded to 0 on-chip. This design also supports programming the chip-address using shift register blocks, where the chip can be assigned a 5-bit address.

·       Auto Burst Mode:

The Local LUT Read SPI command provides auto burst mode. Sending another n times (n=1, 2, 3...) 64 clocks with the chip select signal asserted after the initial command fetches the content of the next LUT address. After LUT address 0x7F, data from LUT address 0x0 is sent. In auto burst mode, the command length becomes 5 + n*2 bytes.

Use cases:

1.       Read 4 channels data of TXV LUT address 0x74 from chip with address 0x0A.

a.   SPI command: 0x6A_80_E8_**_**_**_**_**_**_**_**

b.   Comment: 64 clock cycles when reading only from TXV LUT address 0x74.

Local LUT Write - LCL_LUT_WR

⏵ Requirements: SPI_91

Local LUT Write (LCL_LUT_WR) is a 40-bit (5 bytes) SPI command bounded by the chip select (spi_csb) signal that writes data to the look-up tables (LUTs) of the device.

⏵ Requirements: SPI_80, SPI_4

The Chip Address given in byte1 selects the device to be accessed. If the Chip Address does not match the (pre-configured) chip address, the access will be ignored.

⏵ Requirements: SPI_66, SPI_15, SPI_16

There is a LUT with 128 entries at 64-bit per direction (TX/RX) and polarization (H/V) including four (4) channels at 16-bit per entry. When any of the LUT Pointer (TXV, TXH, RXV or RXH) bit in byte2 is set to 1, access to the associated LUT is enabled. Each LUT location information is completely written with 64 clock pulses (16 bits x 4 channels). When more than one LUT Pointer bit is set to 1, the LUTs are accessed in the following order: TXV -> TXH -> RXV -> RXH.

In general, a complete 64-bit LUT entry including all 4 channels is written with a single write access, starting with channel #1 and followed by channel #2 to #4. In this case the channel select bits ({ CH1, CH0 }) in byte2 must be set to 2'b00. However, if data of a particular channel of a single entry shall only be written, the channel select bits can be set according to the required channel number.

⏵ Requirements: SPI_89, SPI_17

The LUT Address given in byte3 provides the 7-bit address of the LUT to access. Continuous write access and address roll-back is supported. Sending another 64 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command increases the LUT address, and data are received accordingly. When reaching the LUT address 0x7F, the next access targets address 0x0.

⏵ Requirements: SPI_91, SPI_90, SPI_4, SPI_80, SPI_15, SPI_89

The following tables show the LCL_LUT_WR frame structure.

Notes:

·       Chip Address:

Although F641x supports only 4-bit physical address, the digital block supports 5-bit chip address. The top bit is hard coded to 0 on-chip. This design also supports programming the chip-address using shift register blocks, where the chip can be assigned a 5-bit address.

·       Auto Burst Mode:

The Local LUT Write SPI command provides auto burst mode. Sending another n times (n=1, 2, 3...) 64 clocks with the chip select signal asserted after the initial command fetches the content of the next LUT address. After LUT address 0x7F, data from LUT address 0x0 is sent. In auto burst mode, the command length becomes 5 + n*2 bytes.

Use cases:

1.       Write 4 channels data (0x1234_5678_9ABC_DEF1) of TXV LUT address 0x74 to chip with address 0x0A.

a.   SPI command: 0x8A_80_E8_1234_5678_9ABC_DEF1

b.   Comment: 64 clock cycles when writing only to TXV LUT address 0x74.

Global LUT Write - GBL_LUT_WR

⏵ Requirements: SPI_91

Global LUT Write (GBL_LUT_WR) is a 40-bit (5 bytes) SPI command bounded by the chip select (spi_csb) signal that writes data to the look-up tables (LUTs) of the device.

⏵ Requirements: SPI_6, SPI_86

When the Sub-array Enable (SE) bit in byte1 is set to 1, the command is only executed when the Sub-array Index given in the same byte matches the Sub-array Index (SA_INDEX) of the device in the CHIP_INFO register. When SE is set to 0, the command is executed for all devices.

⏵ Requirements: SPI_66, SPI_15, SPI_16

There is a LUT with 128 entries at 64-bit per direction (TX/RX) and polarization (H/V) including four (4) channels at 16-bit per entry. When any of the LUT Pointer (TXV, TXH, RXV or RXH) bit in byte2 is set to 1, access to the associated LUT is enabled. Each LUT location information is completely written with 64 clock pulses (16 bits x 4 channels). When more than one LUT Pointer bit is set to 1, the LUTs are accessed in the following order: TXV -> TXH -> RXV -> RXH.

In general, a complete 64-bit LUT entry including all 4 channels is written with a single write access, starting with channel #1 and followed by channel #2 to #4. In this case the channel select bits ({ CH1, CH0 }) in byte2 must be set to 2'b00. However, if data of a particular channel of a single entry shall only be written, the channel select bits can be set according to the required channel number.

⏵ Requirements: SPI_89, SPI_17

The LUT Address given in byte3 provides the 7-bit address of the LUT to access. Continuous write access and address roll-back is supported. Sending another 64 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command increases the LUT address, and data are received accordingly. When reaching the LUT address 0x7F, the next access targets address 0x0.

⏵ Requirements: SPI_91, SPI_92, SPI_6, SPI_86, SPI_15, SPI_89

The following tables show the LCL_LUT_WR frame structure.

Notes:

·       Auto Burst Mode:

The Global LUT Write SPI command provides auto burst mode. Sending another n times (n=1, 2, 3...) 64 clocks with the chip select signal asserted after the initial command fetches the content of the next LUT address. After LUT address 0x7F, data from LUT address 0x0 is sent. In auto burst mode, the command length becomes 5 + n*2 bytes.

Use cases:

1.       Write 4 channels data (0x1234_5678_9ABC_DEF1) of TXV LUT address 0x74 to chip with sub-array index 0xA.

a.   SPI command: 0xBA_80_E8_1234_5678_9ABC_DEF1

b.   Comment: 64 clock cycles when writing only to TXV LUT address 0x74.

Local Fast Beam Steering - LCL_FBS

⏵ Requirements: SPI_93

Local Fast Beam Steering (LCL_FBS) is basically a 24-bit (3 bytes) SPI command bounded by the chip select (spi_csb) signal and one of the ways to fetch data stored in the LUTs and impress them to the desired channels. There is an exception when both the vertical and horizontal LUT pointer are set, which results in a 4-byte command.

⏵ Requirements: SPI_80, SPI_4, SPI_72

The Chip Address given in byte1 selects the device to be accessed. If the Chip Address does not match the (pre-configured) chip address, the access will be ignored. The Chip Address is increased by 1 internally after each data byte that has been transferred when { PVER, PHOR } is not equal to 2'b00 or every second data byte when { PVER, PHOR } is equal to 2'b00.

⏵ Requirements: SPI_51, SPI_52

The LUT Enable (V_POL_EN, H_POL_EN) bits in byte2 select which polarization will be ON (enabled, powered-up) or OFF (disabled, powered-down). When a LCL_FBS command is issued, the SW_TRX[9:8] bits are updated with the value of the associated LUT Enable bit when latching occurs.

⏵ Requirements: SPI_53

The LUT Pointer (PVER, PHOR) bits in byte2 select the pointer for each polarization. When { PVER, PHOR } = 2b'11, the same LUT address is set for both polarizations. When { PVER, PHOR } = 2b'10, the vertical LUT address is only set. When { PVER, PHOR } = 2b'01, the horizontal LUT address is only set. When { PVER, PHOR } = 2b'00, the vertical LUT pointer is set with the first LUT address and the horizontal LUT pointer with the second address. In this mode data have a width of 16-bits (8 bits for vertical and 8 bits for horizontal).

⏵ Requirements: SPI_20, SPI_97, SPI_98, SPI_70, SPI_107

The Global Latch Enable (GLEN) bit in byte2 selects if the latching is done locally (GLEN=0) or globally (GLEN=1). When GLEN is 0 and { PVER, PHOR } is not equal to 2'b00, data are latched (effective) at the end of each byte. When GLEN is 0 and { PVER, PHOR } is equal to 2'b00, data are latched (effective) at the end of every second byte. Otherwise (GLEN=1), data will be latched after the last data byte that has been transferred with the TRX/GL bit set to 1 in byte3 ({ PVER, PHOR } is not equal to 2'b00) or byte4 ({ PVER, PHOR } is equal to 2'b00). That provides a possibility to keep sending 8-bit data for different V- and H-channels when TRX/GLis set to 0. However, if the TRX/GL bit is not set in any data byte that has been transferred, latching does not occur.

⏵ Requirements: SPI_21, SPI_106, SPI_71

When GLEN is 0, and { PVER, PHOR } is not equal to 2b'00, then the operation mode is set with the TRX/GL bit in byte3. When GLEN is 0, and { PVER, PHOR } is equal to 2b'00, then the operation mode is set with the Tx/Rx/GL (TRX/GL) bit in byte4. The Tx/Rx/GL (TRX/GL) bit in byte3 will be ignored in this case. Otherwise (GLEN=1), the operation mode is set with the TRX bit in byte2.

⏵ Requirements: SPI_22

When CTRL_CFG[0] (TRX_CONT_MODE) bit is set to 1 (SPI control), the SW_TRX[7] (TRX) bit is updated with the value of the

·       Tx/Rx (TRX) bit provided in byte3 if GLEN is 0 and {PVER, PHOR} is not equal to 2b'00.

·       Tx/Rx (TRX) bit provided in byte4 if GLEN is 0 and {PVER, PHOR} is equal to 2b'00.

·       TRX bit in byte2 if GLEN is 1.

⏵ Requirements: SPI_55

When a LCL_FBS command is issued, and CTRL_CFG[0] (TRX_CONT_MODE) bit is set to 0 (external pin configuration), then the operation mode shall remain unchanged independently of the setting in the TRX/GL (GLEN=0) or TRX (GLEN=1) bit to avoid that there is a conflict between the TRX setting in the LCL_FBS command and the external TR pin.

⏵ Requirements: SPI_95, SPI_18

The LUT Address given in byte3 or any following byte provides the 7-bit address of the LUT to access. When any LUT Pointer (PVER, PHOR) bit is set to 1, data from the LUT Address is copied to all four (4) TX/RX Set buffer registers of the selected polarization. There is no provision to load selected channels.

⏵ Requirements: REG_25, REG_27, REG_29, REG_31

When the horizontal LUT pointer (PHOR) is set to 1, the LUT Address that has been accessed is stored in the HLUT_INFO[14:8] bit fields for TX and in HLUT_INFO[6:0] for RX operation mode. When the vertical LUT pointer (PVER) is set to 1, the corresponding bit fields of the VLUT_INFO register are updated with the LUT Address.

⏵ Requirements: SPI_93, SPI_94

The following tables show the LCL_FBS frame structure.

Option 1: When { PVER, PHOR } = 2b'11 or { PVER, PHOR } = 2b'10 or { PVER, PHOR } = 2b'01.

Option 2: When { PVER, PHOR } = 2b'00.

Option 1: When { PVER, PHOR } = 2b'11 or { PVER, PHOR } = 2b'10 or { PVER, PHOR } = 2b'01.

Option 2: When { PVER, PHOR } = 2b'00.

Notes:

·       Bytes: n = 0, 1, 2, 3 …

·       Chip Address:

Although F641x supports only 4-bit physical address, the digital block supports 5-bit chip address. The top bit is hard coded to 0 on-chip. This design also supports programming the chip-address using shift register blocks, where the chip can be assigned a 5-bit address.

Use cases:

1.       Fetch 4 channels data of vertical polarization locally from LUT address 0x74 from chip with address 0x0A and switch to TX-mode with some delay.

a.   SPI command: 0xCA_A8_E9

b.   Comment: V_POL_EN=1, H_POL_EN=0, PVER=1, PHOR=0, DACS=1, GLEN=0, TRX=1.

2.       Fetch 4 channels data of vertical and horizontal polarization locally from LUT address 0x74 from chip with address 0x0A and switch to RX-mode with some delay.

a.   SPI command: 0xCA_F8_E8

b.   Comment: V_POL_EN=1, H_POL_EN=1, PVER=1, PHOR=1, DACS=1, GLEN=0, TRX=0.

Global Fast Beam Steering - GBL_FBS

⏵ Requirements: SPI_93

Global Fast Beam Steering (GBL_FBS) is basically a 24-bit (3 bytes) SPI command bounded by the chip select (spi_csb) signal and one of the ways to fetch data stored in the LUTs and impress them to the desired channels. There is an exception when both the vertical and horizontal LUT pointer are set, which results in a 4-byte command.

⏵ Requirements: SPI_6, SPI_86, SPI_73

When the Sub-array Enable (SE) bit in byte1 is set to 1, the command is only executed when the Sub-array Index given in the same byte matches the Sub-array Index (SA_INDEX) of the device in the CHIP_INFO register. When SE is set to 0, the command is executed for all devices. The Sub-array Index is increased by 1 internally after each data byte that has been transferred when { PVER, PHOR } is not equal to 2'b00 or every second data byte when { PVER, PHOR } is equal to 2'b00. When reaching the sub-array index 0xF, the next access targets Sub-array Index 0x0.

⏵ Requirements: SPI_51, SPI_52

The LUT Enable (V_POL_EN, H_POL_EN) bits in byte2 select which polarization will be ON (enabled, powered-up) or OFF (disabled, powered-down). When a LCL_FBS command is issued, the SW_TRX[9:8] bits are updated with the value of the associated LUT Enable bit when latching occurs.

⏵ Requirements: SPI_53

The LUT Pointer (PVER, PHOR) bits in byte2 select the pointer for each polarization. When { PVER, PHOR } = 2b'11, the same LUT address is set for both polarizations. When { PVER, PHOR } = 2b'10, the vertical LUT address is only set. When { PVER, PHOR } = 2b'01, the horizontal LUT address is only set. When { PVER, PHOR } = 2b'00, the vertical LUT pointer is set with the first LUT address and the horizontal LUT pointer with the second address. In this mode data have a width of 16-bits (8 bits for vertical and 8 bits for horizontal).

⏵ Requirements: SPI_20, SPI_97, SPI_98, SPI_70, SPI_107

The Global Latch Enable (GLEN) bit in byte2 selects if the latching is done locally (GLEN=0) or globally (GLEN=1). When GLEN is 0 and { PVER, PHOR } is not equal to 2'b00, data are latched (effective) at the end of each byte. When GLEN is 0 and { PVER, PHOR } is equal to 2'b00, data are latched (effective) at the end of every second byte. Otherwise (GLEN=1), data will be latched after the last data byte that has been transferred with the TRX/GL bit set to 1 in byte3 ({ PVER, PHOR } is not equal to 2'b00) or byte4 ({ PVER, PHOR } is equal to 2'b00). That provides a possibility to keep sending 8-bit data for different V- and H-channels when TRX/GLis set to 0. However, if the TRX/GL bit is not set in any data byte that has been transferred, latching does not occur.

⏵ Requirements: SPI_21, SPI_106, SPI_71

When GLEN is 0, and { PVER, PHOR } is not equal to 2b'00, then the operation mode is set with the TRX/GL bit in byte3. When GLEN is 0, and { PVER, PHOR } is equal to 2b'00, then the operation mode is set with the Tx/Rx/GL (TRX/GL) bit in byte4. The Tx/Rx/GL (TRX/GL) bit in byte3 will be ignored in this case. Otherwise (GLEN=1), the operation mode is set with the TRX bit in byte2.

⏵ Requirements: SPI_22

When CTRL_CFG[0] (TRX_CONT_MODE) bit is set to 1 (SPI control), the SW_TRX[7] (TRX) bit is updated with the value of the

·       Tx/Rx (TRX) bit provided in byte3 if GLEN is 0 and {PVER, PHOR} is not equal to 2b'00.

·       Tx/Rx (TRX) bit provided in byte4 if GLEN is 0 and {PVER, PHOR} is equal to 2b'00.

·       TRX bit in byte2 if GLEN is 1.

⏵ Requirements: SPI_55

When a GBL_FBS command is issued, and CTRL_CFG[0] (TRX_CONT_MODE) bit is set to 0 (external pin configuration), then the operation mode shall remain unchanged independently of the setting in the TRX/GL (GLEN=0) or TRX (GLEN=1) bit to avoid that there is a conflict between the TRX setting in the GBL_FBS command and the external TR pin.

⏵ Requirements: SPI_95, SPI_18

The LUT Address given in byte3 or any following byte provides the 7-bit address of the LUT to access. When any LUT Pointer (PVER, PHOR) bit is set to 1, data from the LUT Address is copied to all four (4) TX/RX Set buffer registers of the selected polarization. There is no provision to load selected channels.

⏵ Requirements: REG_25, REG_27, REG_29, REG_31

When the horizontal LUT pointer (PHOR) is set to 1, the LUT Address that has been accessed is stored in the HLUT_INFO[14:8] bit fields for TX and in HLUT_INFO[6:0] for RX operation mode. When the vertical LUT pointer (PVER) is set to 1, the corresponding bit fields of the VLUT_INFO register are updated with the LUT Address.

⏵ Requirements: SPI_93, SPI_96

The following tables show the GBL_FBS frame structure.

Option 1: When { PVER, PHOR } = 2b'11 or { PVER, PHOR } = 2b'10 or { PVER, PHOR } = 2b'01.

Option 2: When { PVER, PHOR } = 2b'00.

Option 1: When { PVER, PHOR } = 2b'11 or { PVER, PHOR } = 2b'10 or { PVER, PHOR } = 2b'01.

Option 2: When { PVER, PHOR } = 2b'00.

Notes:

·       Bytes: n = 0, 1, 2, 3 …

Use cases:

The GBL_FBS command is very similar to LCL_FBS. Instead of selecting chips by the chip address, here the command is executed on all chips if SE=0, or with matching Sub-array Index if SE=1. Hence, all LCL_FBS use cases are applicable here as well.

Control Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: SPI_28, SPI_30, SPI_36, SPI_103

Programming of the internal chip address is enabled by setting CTRL_CFG[10] (SHIFTREG_ADDR_PROG) to 1. When programming is terminated, then CTRL_CFG[10] (SHIFTREG_ADDR_PROG) is cleared (set to 0) automatically, and CTRL_CFG[11] (SHIFTREG_ADDR_EN) is set to 1 to indicate that the internal chip address is used. Writing 0 to CTRL_CFG[10] (SHIFTREG_ADDR_PROG) has no effect. CTRL_CFG[11] (SHIFTREG_ADDR_EN) can only be cleared (set to 0) by power-on (porb) or hardware (rstb) reset signal. Refer to section Addressing for more information.

⏵ Requirements: REG_61

Through CTRL_CFG[9] (IO_PROTOCOL) the status of the spib_lvds input pin can be read.

⏵ Requirements: SPI_38, SPI_49, SPI_50

When CTRL_CFG[7] (ERR_DET_EN) is set to 1, the CRC error detection feature is enabled. If the calculated CRC does not correspond to the transmitted CRC, CTRL_CFG[8] (ERR_STATUS_BIT) is asserted (set to 1). Writing 1 to CTRL_CFG[8] clears it. Writing 0 has no meaning. Refer to section Cyclic Redundancy Check for more information.

⏵ Requirements: SPI_38, SPI_49, SPI_50

When CTRL_CFG[6] (TAL_RAL_EN) is set to 1,

⏵ Requirements: REG_4

When CTRL_CFG[5] (RESET) is set to 1, a software reset event is initiated. After reset, CTRL_CFG[5] is cleared (set to 0) automatically. The functionality is the same as for a power-on or hardware reset event with the following exceptions:

·       Scan and IO test mode are not disabled.

·       SPI communication is not reset.

·       The programmable chip address stored in the 8-bit shift register is not initialized to its default value.

⏵ Requirements: REG_14, DFT_17, DFT_18

When CTRL_CFG[4] (IO_TEST) is set to 1, the IO test mode is enabled. When IO test mode is enabled, there is no access to the SPI Interface anymore. To exit IO test mode, a power-on or hardware reset event must be initiated by a minimum 20ns logic low on the porb and rstb pin respectively. Refer to section IO Test for more information.

⏵ Requirements: REG_7

When CTRL_CFG[3] (MANUAL_EN) is set to 1, the enable pin of individual channels (txvN_en, txhN_en, rxvN_en, rxhN_en) can be controlled by CH_ENS register bits. Refer to Figure 18 in section TRX Control for more information.

⏵ Requirements: REG_18, DFT_1, DFT_11, DFT_12

When CTRL_CFG[2] (SCAN_MODE) is set to 1, the scan test mode is enabled. When scan test mode is enabled, there is no access to the SPI Interface anymore. To exit scan test mode, a power-on or hardware reset event must be initiated by a minimum 20ns logic low on the porb and rstb pin respectively. Refer to section Scan Test for more information.

⏵ Requirements: REG_9, IO_5

When CTRL_CFG[1] (SYNC_TRX) is set to 1, FEMs and internal SW are controlled by SW_TRX[7] (TRX) or tr input pin (dependent on CTRL_CFG[0]). Otherwise, they are controlled by the SW_TRX[1:0] ({ TRX_BFH, TRX_BFV}) bit fields. Refer to Figure 19 in section TRX Control for more information.

⏵ Requirements: REG_11, REG_13, REG_70, REG_12

When CTRL_CFG[0] (TRX_CONT_MODE) is set to 1, which is the default value, SW_TRX[7] (TRX) controls the operation mode (1=TX, 0=RX). Otherwise, the tr input signal controls the operation mode. When CTRL_CFG[0] is set to 0, SW_TRX[7] (TRX) is overwritten with the value of the external tr input signal. This way, the state of the tr pin can be read back from this bit.

Overall Chip Configuration Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

The CHIP_INFO register sets the sub-array index of the chip, configures the oscillator, and starts the data transfer from OTP to registers.

⏵ Requirements: IO_2, REG_15, REG_16, IO_8

When set to 1, CHIP_INFO[5] (OSC_EN) enables the oscillator. Otherwise, and by default, the oscillator is disabled. When enabled, the oscillator clock (osc_clk) frequency may vary between 20MHz and 80MHz. CHIP_INFO[7:6] (OSC_FREQ[1:0]) selects the target oscillator frequency by driving the associated osc_freq[1:0] output signals as follows:

·       0x0: 80MHz, 0x1: 40MHz, 0x2: 20MHz, 0x3: OFF.

⏵ Requirements: REG_57, REG_51

When the oscillator gets enabled with the start of an ADC operation or start of the OTP state machine to read all data from the OTP memory to the OTP_DATAn registers, the status of CHIP_INFO[5] is updated accordingly.

⏵ Requirements: REG_17

When set to 1, CHIP_INFO[4] (OTP_FSM_START) starts the OTP state machine to read all data from the OTP memory to the OTP_DATAn registers. This bit is write-only and cleared automatically once the transfer of the OTP bits is completed. Refer to section OTP Memory for more information.

⏵ Requirements: REG_21

CHIP_INFO[3:0] (SA_INDEX[3:0]) stores the sub-array index of the chip that is used for comparison by all global SPI commands when the Sub-array Enable (SE) bit in byte1 of the respective command is set to 1. By default, CHIP_INFO[3:0] is set to 0x0. Refer to sections Global Register Write - GBL_REG_WR, Global LUT Write - GBL_LUT_WR, and Global Fast Beam Steering - GBL_FBS for more information.

Look-up Table Registers

⏵ Requirements: REG_24, REG_26, REG_28, REG_30, REG_71, REG_72, REG_73, REG_74, REG_75, REG_76, REG_77, REG_78, REG_69

There are three (3) different types of Look-up Table registers. These are shown in Figure 10.

·       HLUT_INFO register stores the current (active) LUT pointer (index) for horizontal TX SRAM in bit fields [14:8] (TXH_LUT_IND[6:0]) and for horizontal RX SRAM in bit fields [6:0] (RXH_LUT_IND[6:0]). Equivalent to HLUT_INFO, VLUT_INFO stores the current (active) LUT pointer (index) for vertical TX/RX SRAMs.

·       When the external pin configuration is enabled (CTRL_CFG[0]=0), HLUT_START register defines the start LUT pointer (index) for horizontal TX SRAM in bit fields [14:8] (TXH_LUT_START[6:0]) and for horizontal RX SRAM in bit fields [6:0] (RXH_LUT_START[6:0]).

Equivalent to HLUT_START, VLUT_START defines the start LUT pointer (index) for vertical TX/RX SRAMs.

By default, HLUT_START is set to 0x0 and VLUT_START is set to 0x7F, in this way covering all look-up table range.

These registers are not applicable when SPI control mode is enabled (CTRL_CFG[0]=1).

·       When the external pin configuration is enabled (CTRL_CFG[0]=0), HLUT_STOP register defines the stop LUT pointer (index) for horizontal TX SRAM in bit fields [14:8] (TXH_LUT_STOP[6:0]) and for horizontal RX SRAM in bit fields [6:0] (RXH_LUT_STOP[6:0]).

Equivalent to HLUT_STOP, VLUT_STOP defines the stop LUT pointer (index) for vertical TX/RX SRAMs.

By default, HLUT_START is set to 0x0 and VLUT_START is set to 0x7F, in this way covering all look-up table range.

These registers are not applicable when SPI control mode is enabled (CTRL_CFG[0]=1).

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the registers.

Figure 10: Look-up table registers

⏵ Requirements: REG_25, REG_27, REG_29, REG_31, REG_79, REG_80, REG_81, REG_82, REG_83

Referring to the numbering shown in Figure 10, HLUT/VLUT_INFO registers are updated when

1.       a LCL_FBS or GBL_FBS command is issued.

When the horizontal LUT pointer (PHOR) is set to 1, the LUT Address that has been accessed is stored in the HLUT_INFO[14:8] bit fields for TX and in HLUT_INFO[6:0] for RX operation mode. When the vertical LUT pointer (PVER) is set to 1, the corresponding bit fields of the VLUT_INFO register are updated with the LUT Address.

Refer to sections Local Fast Beam Steering - LCL_FBS and Global Fast Beam Steering - GBL_FBS for more information.

2.       the external pin configuration is enabled by setting CTRL_CFG[0] (TRX_CONT_MODE) to 0.

The HLUT_INFO and VLUT_INFO registers are overwritten with the values of HLUT_START and VLUT_START registers respectively.

3.       the external pin configuration is enabled and there is a 'latch TX/RX+1' or 'TX/RX+1' trigger through the external pins.

Dependent on the operation mode and enabled polarization, either HLUT_INFO [14:8] (tr=1, SW_TRX[9]=1) or VLUT_INFO[14:8] (tr=1, SW_TRX[8]) or HLUT_INFO[6:0] (tr=0, SW_TRX[9]) or VLUT_INFO[6:0] (tr=0, SW_TRX[8]) are automatically incremented by one to reflect the new active LUT index. When reaching the associated HLUT_STOP register value, HLUT_INFO is set to HLUT_START.

Refer to Figure 24 in section External Pin Configuration for more information.

BIST Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: REG_85

BIST[4:3] (SRAM_SEL[1:0]) selects the look-up table (LUT) that is used for initialization, cyclic redundancy check (CRC) or embedded memory self-test (BIST).

⏵ Requirements: REG_86

When set to 1, BIST[2] (SRAM_CRC) triggers a CRC of the content of the LUT (SRAM) that is selected in BIST[4:3]. Refer to section Data Consistency Check for more information. This bit is not cleared automatically, but must be set to 0 by system software.

⏵ Requirements: REG_87

When set to 1, BIST[1] (SRAM_BIST) triggers a BIST of the LUT (SRAM) that is selected in BIST[4:3]. Refer to section Built-in Self Test for more information. This bit is not cleared automatically, but must be set to 0 by system software.

⏵ Requirements: REG_88

When set to 1, BIST[0] (SRAM_INIT) initializes the LUT (SRAM) that is selected in BIST[4:3], and sets all bits to 0. Refer to section Initialization for more information. This bit is not cleared automatically, but must be set to 0 by system software.

⏵ Requirements: REG_89, REG_90

When any of CRC or BIST or LUT (SRAM) initialization is completed, BIST[11] (SRAM_DONE) is set to 1 for the LUT (SRAM) that is selected in BIST[4:3]. If BIST[11] is already set to 1, the status remains unchanged. BIST[11] is cleared (set to 0) for the LUT (SRAM) that is selected in BIST[4:3], if BIST[2:0] is set to 3'b000.

⏵ Requirements: REG_91, REG_92

The number of errors that occured during a BIST is reported in BIST[10:8] (SRAM_ERR[2:0]) for the LUT (SRAM) that is selected in BIST[4:3]. If the number of errors exceeds 7, it is kept as 7. The BIST error counter is cleared (set to 3'b000) for the LUT (SRAM) that is selected in BIST[4:3] when BIST[1] is set to 0.

TRX Switch Control Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: REG_5, REG_6

When set to 1, SW_TRX[11] (MB_EN) enables the chip reference bias. Otherwise, it is disabled. It is possible to read the SW_TRX[11] value on MBIAS[0], too.

⏵ Requirements: REG_8

When SW_TRX[10] (STANDBY) is set to 1, all transmit/receive channels and all DACs are disabled. Refer to Figure 18 in section TRX Control and Figure 22 in section DAC Control for more information.

⏵ Requirements: REG_10

When set to 1, all transmit/receive channels with horizontal (SW_TRX[9]) or vertical (SW_TRX[8]) polarization are enabled. Otherwise, they are disabled. Refer to Figure 18 in section TRX Control for more information.

⏵ Requirements: REG_11, REG_12

When CTRL_CFG[0] (TRX_CONT_MODE) is set to 1, SW_TRX[7] (TRX) selects the operation mode (1=TX, 0=RX). When CTRL_CFG[0] is set to 0, SW_TRX[7] (TRX) is overwritten with the value of the tr input signal. This way, the state of the external TR pin can be read back from this bit.

⏵ Requirements: REG_32, REG_33

The external FEM switches get enabled if the SW_TRX[4] (SW_DRV_EN_TR) bit is set to 1. Dependent on SW_TRX[6] (SW_FEM_TR_MODE) either the positive (SW_TRX[6]=0) or negative (SW_TRX[6]=1) switch is enabled. When an external FEM switch is enabled, dependent on the operation mode SW_TRX[5] (SW_DRV_TR_STATE) defines the level of the output pins. Refer to Figure 20 in section TRX Control for more information.

⏵ Requirements: REG_35, REG_36

When CTRL_CFG[1] (SYNC_TRX) is set to 0, SW_TRX[3:2] ({ TRX_EXTH, TRX_EXTV }) bits select the operation mode (1=TX, 0=RX) of the external FEM switches for vertical (SW_TRX[2]) and horizontal polarization (SW_TRX[3]). Refer to Figure 20 in section TRX Control for more information.

⏵ Requirements: REG_37, REG_38

When CTRL_CFG[1] (SYNC_TRX) is set to 0, SW_TRX[1:0] ({ TRX_BFH, TRX_BFV }) bits enable the BF switches if the operation mode is set to 'TX'. Refer to Figure 19 in section TRX Control for more information.

Chip ID Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: IO_9

Chip ID (CHIP_ID) register is an informational read-only register. It is possible to read the implementation-specific code given by the chip_id[15:0] input signals through the CHIP_ID register. This is shown in Figure 11.

Figure 11: CHIP_ID register input signals connections

MBIAS Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: IO_10

All the bits of this register are directly connected to outputs (digital to analog), and they are used to adjust master bias settings. MBIAS[0] (MB_EN) is an informational read-only bit showing the status of SW_TRX[11] (MB_EN). Setting SW_TRX[11] to 1 is required for the whole chip to be powered up.

ADC Clock Control Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: ADC_2, ADC_3

Based on the CLK_CFG register default settings, the ADC reference clock (adc_clk) is generated based on the following equations:

base_clk = osc_clk/(BASE_CLK_CTRL+1) = osc_clk/(11+1) = osc_clk/12

adc_clk = base_clk/[(ADC_CLK_HIGH+1)+(ADC_CLK_LOW+1)] = base_clk/[(3+1)+(0+1)] = base_clk/5 = osc_clk/60

Whereas,

T(adc_clk, high) = T(base_clk)*(ADC_CLK_HIGH+1) = T(base_clk)*(3+1) = T(base_clk)*4 = T(osc_clk)*48

T(adc_clk, low) = T(base_clk)*(ADC_CLK_LOW+1) = T(base_clk)*(0+1) = T(base_clk)*1 = T(osc_clk)*12

⏵ Requirements: OSC_1, REG_56, REG_16, ADC_1, ADC_5

This is shown in Figure 12. The oscillator gets enabled after writing 1 to any bit of the Sensor Activation 1 (ADC_SRQ1) register when ADC_CFG[10] (ADC_SEL_SOURCE) is set to 0 - refer to the section ADC Controller & Interface for more information - or setting CHIP_INFO[5] (OSC_EN) to 1. There is a wait time of 63 cycles for the oscillator clock to stabilize before adc_clk is output to the ADC with a high to low ratio of 4:1 and the ADC is enabled (adc_en signal driven high).

Figure 12: CLK_CFG register ADC clock generation

⏵ Requirements: ADC_4

Once adc_clk is available, ADC_START_DELAY determines the time (delay) in multiples of adc_clk cycles between the time the ADC is enabled and the start of aquisition phase. With the default value set to 0xF, this would be ADC_START_DELAY+1 = 15+1 = 16 ADC clock cycles.

ADC Control Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: REG_52, REG_53, REG_58

When ADC_CFG[10] (ADC_SEL_SOURCE) is set to 1, the input source of the ADC is selected by ADC_CFG[15:11] (ADC_SEL[4:0]). Otherwise, and by default, it is selected by the Sensor Activation 1 (ADC_SRQ1) register.

⏵ Requirements: REG_54

ADC_CFG[9:7] (ADC_AVG[2:0]) determines the number (n) of data that are used for averaging as follows:

·       n = 1, for ADC_AVG[2:0]=0 (no averaging).

·       n = 2^ADC_AVG, for ADC_AVG[2:0]=1..6.

·       n = 64, for ADC_AVG[2:0]=7.

By default, averaing is enabled, and 64 data are used for averaging (ADC_AVG[2:0]=7).

⏵ Requirements: REG_55, REG_66

When ADC_CFG[6] (PD_DIFF_MODE) is set to 1, PDET data are stored as measured (and after averaging). Otherwise, and by default, the difference of PREF and PDET (PREF-PDET) is stored. When ADC_CFG[6] is set to 0, and the result of PREF-PDET is less than zero, 0x0 is stored.

⏵ Requirements: IO_16

All other bits, ADC_CFG[5:0], are connected straight to output signals for configuring the ADC. This is shown in Figure 13.

Figure 13: ADC_CFG register to output signals connections

Sensor Enable Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: IO_17, REG_59

The Sensor Enable (SENSOR_EN) register drives the enable pins (sensor_en[15:0]) for miscellaneous sensors on the chip. By default, the value of the SENSOR_EN register is 0x0 (no sensor enabled).

⏵ Requirements: REG_60, REG_64

When ADC_CFG[10] (ADC_SEL_SOURCE) is set to 0, writing 1 to any bit of the Sensor Activation 1 (ADC_SRQ1) register sets the associated bit in the SENSOR_EN register, and this way enables the selected sensor(s). Once the ADC operation of all selected channels is completed, the SENSOR_EN register is cleared (set to 0x0, all sensors disabled). Refer to section ADC Controller & Interface for more information.

When ADC_CFG[10] (ADC_SEL_SOURCE) is set to 1, the selected sensor must be enabled manually before the measurement is started by writing 1 to the associated bit in the SENSOR_EN register. Similarly, the selected sensor must be disabled by writing 0 once the ADC operation is completed.

⏵ Requirements: IO_23

The sensor bias enable (sensor_bias_en) output signal is driven high when any of SENSOR_EN[9:0] are 1.

Sensor Configuration Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: REG_62, REG_67

SENSOR_CFG[13:12] (TSENS_POL_CFG[1:0]) selects the setting that is used for temperature sensor measurements. This setting is applicable independently of the mode selection in ADC_CFG[10] (ADC_SEL_SOURCE).

·       When set to 2'b00, two measurements, TSENS_POL0 and TSENS_POL1, are executed. In the first measurement d_tsens_pol is driven low, and in the second measurement it is driven high.

·       When set to 2'b01, two measurements, TSENS_POL0 and TSENS_POL1, are executed, and in both measurements d_tsens_pol is driven low.

·       When set to 2'b10, two measurements, TSENS_POL0 and TSENS_POL1, are executed, and in both measurements d_tsens_pol is driven high.

·       When set to 2'b11, the same procedure is executed as for 2'b00.

⏵ Requirements: IO_18

Besides that, all bits (SENSOR_CFG[15:0]) are connected straight to output signals for configuring the on-chip sensors. This is shown in Figure 14.

Figure 14: SENSOR_CFG register to output signals connections

SCRATCH Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: REG_50

2 bytes of memory for arbitrary data storage. This data does not affect the operation of the device.

TRX Setting Registers

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: REG_3, IO_43, IO_44

Data written to the TXVn/TXHn/RXVn/RXHn_SET (n = 1..4) registers is initially stored in the TXVn/TXHn/RXVn/RXHn_SET buffer registers. The data update can either be done with

·       a LCL_REG_WR or GBL_REG_WR command through the SPI interface, or

·       a 'latch TX/RX+1' trigger through the external pins - refer to Figure 24 in section External Pin Configuration for more information.

⏵ Requirements: SPI_8, IO_41

Transfer of data from the TXVn/TXHn_SET buffer registers to the active registers is initiated

·       when the TX RF Load (TRL) bit in byte3 of a LCL_REG_WR or GBL_REG_WR command is set to 1.

·       when external pin configuration is enabled (CTRL_CFG[0]=0), and

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x6 or 0x9, and there is a transition on tload from 0 to 1 (rising edge).

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x3 or 0xC, and tr is set to 1, and there is a transition on rload from 0 to 1 (rising edge).

⏵ Requirements: SPI_9, IO_42

Transfer of data from the RXVn/RXHn_SET buffer registers to the active registers is initiated

·       when the RX RF Load (RRL) bit in byte3 of a LCL_REG_WR or GBL_REG_WR command is set to 1.

·       when external pin configuration is enabled (CTRL_CFG[0]=0), and

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x6 or 0x9, and there is a transition on rload pin from 0 to 1 (rising edge).

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x3 or 0xC, and tr is set to 0, and there is a transition on tload pin from 0 to 1 (rising edge).

⏵ Requirements: IO_43

Transfer of data from the active TXVn/TXHn LUT index + 1 to both TXVn/TXHn_SET buffer and active registers is initiated

·       when external pin configuration is enabled (CTRL_CFG[0]=0), and

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x4 or 0x5 or 0x7 or 0x8, and there is a transition on tload from 0 to 1 (rising edge), or

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x1 or 0x2 or 0xA or 0xB, and tr is set to 1, and there is a transition on rload from 0 to 1 (rising edge).

⏵ Requirements: IO_44

Transfer of data from the active RXVn/RXHn LUT index + 1 to both RXVn/RXHn_SET buffer and active registers is initiated

·       when external pin configuration is enabled (CTRL_CFG[0]=0), and

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x4 or 0x5 or 0x7 or 0x8, and there is a transition on rload from 0 to 1 (rising edge), or

o    PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x1 or 0x2 or 0xA or 0xB, and tr is set to 0, and there is a transition on tload from 0 to 1 (rising edge).

Once the active registers are updated, the TX/RX outputs change to their new values.This is shown in Figure 15 taking the example of TX.

Figure 15: TX/RX register to output signal connections

⏵ Requirements: REG_63

As for the data in the TXVn/TXHn/RXVn/RXHn_OFFSET (for n = 1; n <= 4) registers, the phase offset (TX/RX_PH_OFF) is stored in twos (2s) complement format, whereas channel bias (TX/RX_CH_BIAS) and align offset (TX/RX_ALIGN_OFF) are stored as absolute values.

⏵ Requirements: REG_102, REG_103

The TXVn_SET (n=1..4) output register values are generated according to the following equations, taking TX operation mode with vertical polarization as an example. The equations for TXHn_SET, RXVn_SET, and RXHn_SET output registers are equivalent.

TXVn_SET[15:10] (output) = TXVn_SET[15:10] (buffer) +/- TXVn_OFFSET[7:4]

TXVn_SET[9:0] (output) = TXVn_SET[9:0] (buffer)

Whereas,

N = n = 1..4.

⏵ Requirements: IO_35

If the result of TXVn_SET[15:10] (buffer) + TXVn_OFFSET[7:4] is greater than 64, the overflow is ignored (in decimal it would be TXVn_SET[15:10] (buffer) + TXVn_OFFSET[7:4] - 64). The same method is applied if the result of TXHn_SET[15:10] (buffer) + TXHn_OFFSET[7:4], RXVn_SET[15:10] (buffer) + RXVn_OFFSET[7:4] (buffer) or RXHn_SET[15:10] (buffer) + RXHn_OFFSET[7:4] is greater than 64.

⏵ Requirements: IO_36

If the result of TXVn_SET[15:10] (buffer) - TXVn_OFFSET[7:4] is less than 0, than d'64 is added (in decimal it would be TXVn_SET[15:10] (buffer) - TXVn_OFFSET[7:4] + 64). The same method is applied if the result of TXHn_SET[15:10] (buffer) - TXHn_OFFSET[7:4], RXVn_SET[15:10] (buffer) + RXVn_OFFSET[7:4] or RXHn_SET[15:10] (buffer) + RXHn_OFFSET[7:4] is less than 0.

⏵ Requirements: SPI_74

When there is a LCL_REG_RD command to a TXVn/TXHn/RXVn/RXHn_SET register, the content of the active register is read.

⏵ Requirements: REG_94

[OPTIONAL] The host has the option to read from either the TXVn/TXHn/RXVn/RXHn_SET buffer, active or output register when accessing theTXVn/TXHn/RXVn/RXHn_SET registers. The TX/RX read back option is configured by the CTRL_CFG[14:13] (READBACK[1:0]) bits. By default, the host reads from the active register.

⏵ Requirements: IO_14, IO_26, IO_34, IO_15, IO_27, IO_28, IO_29

As shown in Figure 15, all TXVn/TXHn/RXVn/RXHn SET output register bits are connected straight to output signals. This applies also to the TXCOM/RXCOM_BIAS2, TXCOM/RXCOM_BIAS1, TXCOM/RXCOM_CFG, and TXCOM/RXCOM_TUNE registers values, which are used to compile the common TX/RX setting output signals, as well as for TXVn/TXHn/RXVn/RXHn_OFFSET register bits [15:8] and [3:0]:

txvN/txhN/rxvN/rxhN_set[63:0] = TXVn/TXHn/RXVn/RXHn_SET[15:0]

txvN/txhN/rxvN/rxhN_spare[4:0] = TXVn/TXHn/RXVn/RXHn_OFFSET[15:11]

txvN/txhN/rxvN/rxhN_bias[2:0] = TXVn/TXHn/RXVn/RXHn_OFFSET[10:8]

txvN/txhN/rxvN/rxhN_off[3:0] = TXVn/TXHn/RXVn/RXHn_OFFSET[3:0]

tx/rx_com[63:0] = { TXCOM/RXCOM_BIAS2[15:0], TXCOM/RXCOM_BIAS1[15:0], TXCOM/RXCOM_CFG[15:0], TXCOM/RXCOM_TUNE[15:0] }

TRX Spare Register

Refer to the 'Register Map/Descriptions' or click here to see a detailed description of the register.

⏵ Requirements: IO_25

The TRX Spare (TX_RX_SPARE) register drives some spare pins (spare[15:0]) for TX/RX channels. By default, the value of the TX_RX_SPARE register is 0x0.

Reading Fuses

⏵ Requirements: REG_44

With this sequence, a read of 8 bits is done simultaneously. The status of the selected fuses (otp_din[7:0]) is latched when OTP_CFG[13] (OTP_DIN_LATCH) is set to 1, whereas OTP_DATAn = { otp_data[n], otp_data[n-1] }.

⏵ Requirements: REG_46

The read current level is being selected by two bits OTP_CFG[3:2] (OTP_CUR[1:0]). These bits are used for examining the robustness of the read. The purpose of these two bits is to ensure a robust read over temperature and voltage range even when the test is done in a single voltage and at a room temperature. In normal operation OTP_CUR[1:0]=2'b01. If a burned fuse is measured one would like to perform a measurement in a lower current to ensure that the fuse is being read as a burned one even with the lower current. In this case OTP_CUR[1:0]=2'b00 will be selected as a robustness of the read test. This function ensures that there is enough margin for avoiding the need to test the module over the whole temperature range. When a “non-burned” fuse is read, one would like to perform a test with a higher current to ensure that the fuse is read as an un-burned fuse with higher current. In this case OTP_CUR[1:0]=2'b10 is selected as a robustness read test.

When reading from the OTP memory, the OTP_CFG register bits must be set according to the sequence shown in Figure 28, at the same time respecting the timing requirements set forth in Table 5. Even though there are no concrete timing requirements, OTP power-on reset (OTP_POR) and program enable (OTP_PROG) must be set before the OTP memory is enabled (OTP_EN set to 1).

Figure 28: OTP memory register read access (option 1)

With reference to Figure 28, Table 5 shows the timing characteristics of the OTP memory for read access, unless otherwise noted.

Table 5: OTP memory read AC characteristics

Another option for reading data from the OTP memory is shown in Figure 29. The OTP_READ is continuously asserted (set to 1) for the whole read access, and only OTP_RW_ACCESS is changing its value. The timing characteristics specified in Table 5 are applicable for this option, too.

Figure 29: OTP memory register read access (option 2)

Programming Fuses

With this sequence, a selected fuse is being burned. The selection of the fuse is done by the following register bits:

·       OTP_CFG[12:10] (OTP_WR_BIT[2:0]) selects one out of 16 8-bit banks.

·       OTP_CFG[9:6] (OTP_RW_ADDRESS[3:0]) selects the bit within the bank to be burned.

When programming the OTP memory, the OTP_CFG register bits must be set according to the sequence shown in Figure 30, at the same time respecting the timing requirements set forth in Table 6. Even though there are no concrete timing requirements, OTP power-on reset (OTP_POR) and enable (OTP_EN) must be set before or at the same time OTP read (OTP_READ) is set to 0.

Figure 30: OTP memory register programming

With reference to Figure 30, Table 6 shows the timing characteristics of the OTP memory for programming, unless otherwise noted.

Table 6: OTP memory write AC characteristics

Overview

⏵ Requirements: DFT_13, DFT_15

IO test structures are inserted into the Digital Subsystem for spi_csb, spi_clk, spi_mosi_in, spi_mosi_out, add_in[3:0], tr, tload, rload and stdby. rstb is excluded from the IO test, because any input low value will issue a hardware reset.

⏵ Requirements: DFT_14

The test structures are used for testing and characterizing the following features:

·       General input and output functional operation.

·       Input and output voltage levels.

·       Input leakage current.

⏵ Requirements: DFT_16, DFT_17, DFT_18

IO test is enabled by setting CTRL_CFG[4] (IO_TEST) to 1. When IO test mode is enabled, there is no access to the SPI Interface anymore. To exit IO test mode, a power-on or hardware reset event must be initiated by a minimum 20ns logic low on the porb and rstb pin respectively.

Functional Description

This section describes some of the operations or implementation-defined features of the IO test. The topics in this section are:

·       Input Characteristics

·       Output Characteristics

Input Characteristics

For testing the input characteristics of the single-ended IO buffers, all input pins of the SPI interface (spi_csb, spi_clk, spi_mosi_in, add_in[4:0]) and control pins (tr, tload, rload, stdby) are OR-ed and output on spi_miso_out. This is shown in Figure 31.

Make sure that only one input pin is driven at a time and single-ended signaling (spib_lvds=0) is selected.

Figure 31: IO test input characteristics

For testing the input characteristics of the LVDS buffers, the setup shown in Figure 31 can be reused. This is shown in Figure 32 taking the SPI clock as an example. Make sure that except SCLK and ADD3 all other input pins are driven low and differential signaling (spib_lvds=1) is selected.

Figure 32: IO test LVDS buffer

Output Characteristics

The SPI data output (spi_miso_out) pin can be tested when testing the input characteristics.

The address output (add_in_1_data) pin can be tested when the internal chip address is programmed. Refer to section Addressing for more information.

Input Delay

⏵ Requirements: SPI_59

The SPI master drives data (MOSI) on the falling edge of SCLK. MOSI and SCLK shall be synchronized as much as possible, and MOSI output delay [tod(MOSI)] should be less than 1ns. The board delay is assumed to be 1ns for SCLK [tld(SCLK)] and 2ns for MOSI [tld(MOSI)] (considering a board delay skew between SCLK and MOSI of 1ns). F641X input buffer delay for both SCLK [tio(SCLK)] and SDI [tio(SDI)] is less than 1ns. Data is captured on the rising edge of SCLK. This is shown in Figure 37.

Figure 37: SPI input timing

With reference to Figure 3 and Table 1 the SDI (input data) setup time tsu(SDI) is specified as follows:

tsu(SDI) = tpl(SCLK) - tod(MOSI) - [tld(MOSI) - tld(SCLK)] - [tio(SDI) - tio(SCLK)] = 4ns - 1ns - [2ns - 1ns] - [1ns - 1ns] = 2ns

Output Delay

⏵ Requirements: SPI_60

F641X drives data (SDO) on the falling edge of SCLK. With a board delay of 1ns for SCLK [tld(SCLK)] and SDO [tld(SDO)] each, the data (MOSI) setup time [tsu(MOSI)] at the SPI master is 2ns. This is shown in Figure 38.

Figure 38: SPI output timing

With reference to Figure 3 and Table 1 the SDO (output data) delay time tod(SDO) is specified as follows:

tod(SDO) = tpl(SCLK) - tld(SCLK) - tld(SDO) - tsu(MISO) = 9ns - 1ns - 1ns - 2ns = 5ns

Whereas,

tod(spi_miso_out) = tod(SDO) - tio(SCLK) - tio(SDO) = 5ns - 1ns - 1ns = 3ns