F641x Digital
Technical Requirement Specification Rev.544
Terms, Definitions and Abbreviations
Terms and Definitions
Requirement Naming Conventions
Requirement: mandatory quality or feature, qualified by the verbs "SHALL", "MUST", "SHALL NOT", "MUST NOT".
Recommendation: desirable yet optional quality or feature, qualified by the verbs "SHOULD", "SHOULD NOT".
Indication of options without preference: "MAY".
Indication of actual or assumed situation (for example assumptions, limitations): "IS", "IS NOT", "WILL BE", "WILL NOT BE", …
Terminology
The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and "OPTIONAL" in this document are to be interpreted as described in BCP 14 [RFC 2119, March 1997]:
MUST: This word, or the terms "REQUIRED" or "SHALL", mean that the definition is an absolute requirement of the specification.
MUST NOT: This phrase, or the phrase "SHALL NOT", mean that the definition is an absolute prohibition of the specification.
SHOULD: This word, or the adjective "RECOMMENDED", mean that there may exist valid reasons in particular circumstances to ignore a particular item, but the full implications must be understood and carefully weighed before choosing a different course.
SHOULD NOT: This phrase, or the phrase "NOT RECOMMENDED" mean that there may exist valid reasons in particular circumstances when the particular behavior is acceptable or even useful, but the full implications should be understood and the case carefully weighed before implementing any behavior described with this label.
MAY: This word, or the adjective "OPTIONAL", mean that an item is truly optional. One vendor may choose to include the item because a particular marketplace requires it or because the vendor feels that it enhances the product while another vendor may omit the same item. An implementation which does not include a particular option MUST be prepared to interoperate with another implementation which does include the option, though perhaps with reduced functionality. In the same vein an implementation which does include a particular option MUST be prepared to interoperate with another implementation which does not include the option (except, of course, for the feature the option provides.)
When it is decided that a specific requirement is not supported, it will be indicated in strike-through font.
Digital Subsystem
Overview
This chapter lists the system requirements for the Digital Subsystem functions.
This chapter contains the following sections:
· SPI - General SPI Requirements
· SPI - Data Transfer Protocol Requirements
· SPI - (Programmable) Chip Address
· SPI - Cyclic Redundancy Check (CRC)
· REG - General Register Requirements
· REG - H/VLUT_INFO/START/STOP Registers
· REG - BIST/CRC_RESULT Registers
· IO - Common TX/RX Settings Signals
Functional Requirements
SPI - General SPI Requirements
⏵ SPI_1
SPI shall support the commands (data transfer protocols) set forth in worksheet "SPI Commands".
⏵ SPI_2
SPI shall support a 4-pin protocol, using spi_clk, spi_csb, spi_miso_out/spi_miso_oe, and spi_mosi_in.
⏵ SPI_3
SPI shall provide the user full access to all registers of the F641X.
⏵ SPI_61
After a reset, the SPI data output enable signal (spi_miso_oe) shall be set to 0 and the data output (SDO) tri-stated accordingly.
⏵ SPI_63
Data in signals (spi_mosi_in) shall be sampled on the rising edge of the serial clock (spi_clk) with the chip select (spi_csb) signal asserted. The sampling edge shall be fixed and cannot be changed.
⏵ SPI_47
Data sampling shall be stopped when the chip select (spi_csb) signal is deasserted.
⏵ SPI_64
Data out signals (spi_miso_out) shall be driven on opposite (falling) edge than sampling edge. The behavior shall be fixed and cannot be changed.
SPI - Data Transfer Protocol Requirements
⏵ SPI_78
The Local Register Read (LCL_REG_RD) command shall basically comprise of 4 bytes, whereas byte1 and byte2 shall be sent by the SPI master and byte3 and byte4 shall be the Register Read Data returned by F641X.
Note: Referring to SPI_5, it is possible that F641X sends 2n (n=1,2,3...) additional bytes to the SPI master.
⏵ SPI_79
For Local Register Read (LCL_REG_RD) command, Mode shall be set to 3'b000.
⏵ SPI_80
The Chip Address given in byte1 of the LCL_REG_RD/WR, LCL_LUT_RD/WR or LCL_FBS command shall select the chip to be accessed by the associated SPI command.
⏵ SPI_81
The Register Address given in byte2 of the LCL_REG_RD/WR or GBL_REG_WR command shall provide the 8-bit address of the internal register to access.
⏵ SPI_4
If the chip address given in byte1 of the LCL_REG_RD/WR, LCL_LUT_RD/WR or LCL_FBS command does not match the (pre-configured) chip address, the access shall be ignored.
Exception: Requirements SPI_8 and SPI_9 shall be applicable even if there is a mismatch in the chip address.
⏵ SPI_5
Continuous read/write access and address roll-back shall be supported for the following commands: LCL_REG_RD/WR and GBL_REG_WR.
Sending another 16 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command shall increase the register address, and data shall be received/transmitted accordingly.
When reaching the register address 0xFF, the next access shall target address 0x0.
⏵ SPI_74
When there is a LCL_REG_RD command to a buffered registers, the content of the active register shall be read.
⏵ SPI_82
For Local Register Write (LCL_REG_WR) command, Mode shall be set to 3'b001.
⏵ SPI_85
For Global Register Write (GBL_REG_WR) command, Mode shall be set to 3'b010.
⏵ SPI_83
The Local and Global Register Write (LCL/GBL_REG_WR) command shall basically comprise of 5 bytes.
Note: Referring to SPI_5, it is possible that F641X receives 2n (n=1,2,3...) additional bytes from the SPI master.
⏵ SPI_62
For all writes, data shall be committed in halfwords as the sixteen data bit of a data field. If the write access is not an even multiple of 16 clocks, the trailing data bits shall not be committed.
Exception: When { PSS, GAS } = 2b'10 or { PSS, GAS } = 2b'10 in byte3 of the LCL_REG_WR or GBL_REG_WR command, data shall be committed in bytes as the eight data bit of a data field. If the write access is not an even multiple of 8 clocks, the trailing data bits shall not be committed.
⏵ SPI_6
When the Sub-array Enable (SE) bit in byte1 of the GBL_REG_WR, GBL_LUT_WR or GBL_FBS command is set to 1, the command shall only be executed when the Sub-array Index given in the same byte matches the Sub-array Index (SA_INDEX) for the chip in the CHIP_INFO register.
Exception: Requirements SPI_8 and SPI_9 shall be applicable even if there is a mismatch in the sub-array index.
⏵ SPI_86
When the Sub-array Enable (SE) bit in byte1 of the GBL_REG_WR command is set to 0, the command shall be executed for all devices.
⏵ SPI_8
When the TX RF Load (TRL) bit in byte3 of the LCL_REG_WR or GBL_REG_WR command is set to 1, data of the TXVn and TXHn Set (TXVn/TXHn_SET, n = 1..4) buffer registers shall be transferred to the TXVn_SET and TXHn_SET active registers respectively.
This behavior shall be independent of the CTRL_CFG[0] (TRX_CONT_MODE) setting.
⏵ SPI_9
When the RX RF Load (RRL) bit in byte3 of the LCL_REG_WR or GBL_REG_WR command is set to 1, data of the RXVn and RXHn Set (RXVn/RXHn_SET, n = 1..4) buffer registers shall be transferred to the RXVn_SET and RXHn_SET active registers respectively.
This behavior shall be independent of the CTRL_CFG[0] (TRX_CONT_MODE) setting.
⏵ SPI_65
The data transfer described in SPI_8..9 shall be initiated even if the chip address or sub-array index given in byte1 does not match the (pre-configured) chip address and CHIP_INFO[3:0] respectively.
Note: As for the chip address, refer to section '(Programmable) Chip Address' for more information.
⏵ SPI_10
When none of the RF Load bits in byte3 of the LCL_REG_WR or GBL_REG_WR command are set to 1, then there shall be no data transfer from buffer to active registers.
⏵ SPI_67
When
- the DACs are enabled in the PA_LNA_DAC_CFG3 register, and
- Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high, and
- CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (SPI control), and
- the operating mode is set to 'TX', and
- CTRL_CFG[6] (TAL_RAL_EN) is set to 1
setting the TX DAC Load (TAL) bit in byte3 of a LCL_REG_WR or GBL_REG_WR command to 1 shall switch all PA DACs to the DAC ON state.
Setting the TAL bit to 0 shall switch the PA DACs to the PA DAC OFF state.
Note: When enabled, corresponding PA DAC outputs are set as DAC_ONn register. When disabled, the outputs are set as PA_DAC_OFF register.
⏵ SPI_68
When
- the DACs are enabled in the PA_LNA_DAC_CFG3 register, and
- Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high, and
- CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (SPI control), and
- the operating mode is set to 'RX', and
- CTRL_CFG[6] (TAL_RAL_EN) is set to 1
setting the RX DAC Load (RAL) bit in byte3 of a LCL_REG_WR or GBL_REG_WR command to 1 shall switch all LNA DACs to the DAC ON state.
Setting the RAL bit to 0 shall switch the LNA DACs to LNA DAC OFF state.
Note: When enabled, corresponding LNA DAC outputs are set as DAC_ONn register. When disabled, the outputs are set as LNA_DAC_OFF register.
⏵ SPI_101
Requirement removed.
⏵ SPI_99
Requirement removed.
⏵ SPI_102
Requirement removed.
⏵ SPI_84
Switching the DACs as described in SPI_67..68 shall be done even if the chip address or sub-array index given in byte1 does not match the (pre-configured) chip address and CHIP_INFO[3:0] respectively.
Note: As for the chip address, refer to section '(Programmable) Chip Address' for more information.
⏵ SPI_77
Requirement removed.
⏵ SPI_11
When both PSS and GAS bits are set to 0 ({ PSS, GAS } = 2b'00) in byte3 of the LCL_REG_WR or GBL_REG_WR command , then 16-bit data shall be provided in byte4 and byte5 as well as in all subsequent halfwords (if any).
Note: With this configuration (setting) it is expected that data are written to registers other than TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET (n = 1..4). When writing to TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET registers with this setting, proper device operation is not guaranteed anymore.
⏵ SPI_12
When PSS bit is set to 1 and GAS bit is set to 0 ({ PSS, GAS } = 2b'10) in byte3 of the LCL_REG_WR or GBL_REG_WR command, then 8-bit data shall be provided in byte4 and all subsequent bytes (if any) corresponding to TX_PHASE_CTRL and RX_PHASE_CTRL bit fields respectively.
Note: With this configuration (setting) it is expected that phase set data only are written to TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET (n = 1..4) registers. When writing to any other register with this setting, proper device operation is not guaranteed anymore.
⏵ SPI_13
When PSS bit is set to 0 and GAS bit is set to 1 ({ PSS, GAS } = 2b'01) in byte3 of the LCL_REG_WR or GBL_REG_WR command, then 8-bit data shall be provided in byte4 and all subsequent bytes (if any) corresponding to TX_GAIN_CTRL and RX_GAIN_CTRL bit fields respectively.
Note: With this configuration (setting) it is expected that gain set data only are written to TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET (n = 1..4) registers. When writing to any other register with this setting, proper device operation is not guaranteed anymore.
⏵ SPI_14
Requirement removed.
⏵ SPI_75
When both PSS and GAS bits are set to 1 ({ PSS, GAS } = 2b'11) in byte3 of the LCL_REG_WR or GBL_REG_WR command, then 16-bit data shall be provided in byte4 and byte5 as well as in all subsequent halfwords (if any).
Note: With this configuration (setting) it is expected that data (both phase and gain) are written to TXVn_SET/TXHn_SET/RXVn_SET/RXHn_SET (n = 1..4) registers. When writing to any other register with this setting, proper device operation is not guaranteed anymore.
⏵ SPI_104
When the Cyclic Redundancy Check (CRC) error detection feature is enabled, then { NB1, NB0 } bits in byte3 of the LCL_REG_WR or GBL_REG_WR command shall determine the number of data bytes that are transmitted:
2'b00: 2 bytes when{ PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11. Otherwise, 1 byte.
2'b10: 8 bytes when { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11. Otherwise, 4 bytes.
2'b10: 16 bytes when { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11. Otherwise, 8 bytes.
2'b11: 32 bytes when { PSS, GAS } = 2b'00 or { PSS, GAS } = 2b'11. Otherwise, 16 bytes.
⏵ SPI_105
When the Cyclic Redundancy Check (CRC) error detection feature is disabled, then { NB1, NB0 } bits in byte3 of the LCL_REG_WR or GBL_REG_WR command shall be ignored.
⏵ SPI_87
The Local LUT Read (LCL_LUT_RD) command shall basically comprise of 5 bytes, whereas byte1 through byte3 shall be sent by the SPI master and byte4 and byte5 shall be the LUT Read Data returned by F641X.
Note: Referring to SPI_5, it is possible that F641X sends 2n (n=1,2,3...) additional bytes to the SPI master.
⏵ SPI_88
For Local LUT Read (LCL_LUT_RD) command, Mode shall be set to 3'b011.
⏵ SPI_66
There shall be a LUT with 128 entries at 16-bit per direction (TX/RX), polarization (H/V) and channel (1..4), which are 128 x 2 x 2 x 4 = 2,048 entries in total.
⏵ SPI_15
When any of the LUT Pointer (TXV, TXH, RXV or RXH) bit in byte2 of the LCL_LUT_RD, LCL_LUT_WR or GBL_LUT_WR command is set to 1, access to the associated LUT shall be enabled.
⏵ SPI_16
When more than one LUT Pointer (TXV, TXH, RXV or RXH) bit in byte2 of the LCL_LUT_RD, LCL_LUT_WR or GBL_LUT_WR command is set to 1, the LUTs shall be accessed in the following order: TXV -> TXH -> RXV -> RXH.
⏵ SPI_17
Continuous read/write access and address roll-back shall be supported for the following commands: LCL_LUT_RD, LCL_LUT_WR or GBL_LUT_WR.
Sending another 64 clock (spi_clk) cycles with the chip select (spi_csb) signal asserted after the initial command shall increase the LUT address, and data shall be received/transmitted accordingly.
When reaching the LUT address 0x7F, the next access shall target address 0x0.
⏵ SPI_51
The LUT Enable (V_POL_EN, H_POL_EN) bits in byte2 of the LCL_FBS or GBL_FBS command shall select which polarization will be ON (enabled, powered-up) or OFF (disabled, powered-down):
- V_POL_EN=H_POL_EH=1 shall enable both polarizations.
- V_POL_EN=1, H_POL_EH=0 shall enable only vertical polarization.
- V_POL_EN=0, H_POL_EH=1 shall enable only horizontal polarization.
- V_POL_EN=0, H_POL_EH=0 shall disable both polarizations.
⏵ SPI_52
When a LCL_FBS or GBL_FBS command is issued, the SW_TRX[9:8] ({ H_POL_EN, V_POL_EN }) bits shall be updated with the value of the associated LUT Enable (V_POL_EN, H_POL_EH) bit provided in byte2 when latching occurs.
⏵ SPI_53
The LUT Pointer (PVER, PHOR) bits in byte2 of the LCL_FBS or GBL_FBS command shall select the pointer for each polarization:
- PVER=PHOR=1, shall set the same LUT address for both polarizations.
- PVER=1, PHOR=0 shall set only the vertical LUT address.
- PVER=0, PHOR=1 shall set only the horizontal LUT address.
- PVER=PHOR=0, the vertical LUT pointer shall be set with the first LUT address and the horizontal LUT pointer with the second address. In this mode data shall have a width of 16-bits (8 bits for vertical and 8 bits for horizontal).
⏵ SPI_89
The LUT Address given in byte3 of the LCL_LUT_RD, LCL_LUT_WR, or GBL_LUT_WR command shall provide the 7-bit address of the LUT to access.
⏵ SPI_90
For Local LUT Write (LCL_LUT_WR) command, Mode shall be set to 3'b100.
⏵ SPI_91
The Local and Global LUT Write (LCL/GBL_LUT_WR) commands shall basically comprise of 5 bytes.
Note: Referring to SPI_17, it is possible that F641X receives 2n (n=1,2,3...) additional bytes from the SPI master.
⏵ SPI_92
For Global LUT Write (GBL_LUT_WR) command, Mode shall be set to 3'b101.
⏵ SPI_93
The Local (LCL_FBS) and Global (GBL_FBS) Fast Beam Steering command shall basically comprise of 3 bytes. There is an exception when { PVER, PHOR } is set to 2b'00, which shall result in a 4-byte command.
⏵ SPI_94
For Local Fast Beam Steering (LCL_FBS) command, Mode shall be set to 3'b110.
⏵ SPI_72
As for a LCL_FBS command, the device address provided in byte1 shall be increase by 1 internally after each data byte (if { PVER, PHOR } is not equal to 2'b00) or every second data byte (if { PVER, PHOR } is equal to 2'b00) that has been transferred. When reaching the device address 0xF, the next access shall target device address 0x0.
⏵ SPI_73
As for a GBL_FBS command, the sub-array index provided in byte1 shall be increase by 1 internally after each data byte (if { PVER, PHOR } is not equal to 2'b00) or every second data byte (if { PVER, PHOR } is equal to 2'b00) that has been transferred. When reaching the sub-array index 0xF, the next access shall target sub-array index 0x0.
⏵ SPI_54
Requirement removed.
⏵ SPI_18
When any LUT Pointer (PVER, PHOR) bit in byte2 of the LCL_FBS or GBL_FBS command is set to 1, data from the address given in byte3 is copied from the LUT to all four (4) TX/RX Set buffer registers of the selected polarization.
⏵ SPI_19
Requirement removed.
⏵ SPI_20
The Global Latch Enable (GLEN) bit in byte2 of the LCL_FBS or GBL_FBS command shall select if the latching will be done locally (GLEN = 0) or globally (GLEN = 1).
⏵ SPI_97
When GLEN is 0 and { PVER, PHOR } is not equal to 2'b00, data shall be effective at the end of each byte. When GLEN is 0 and { PVER, PHOR } is equal to 2'b00, data shall be effective at the end of every second byte.
⏵ SPI_98
When GLEN is 1, the data shall be effective after the last data byte that has been transferred with the TRX/GL bit in byte3 set to 1.
Note: Setting GLEN to 1 provides a possibility to keep sending 8-bit data for different V- and H-channels. However, if the TRX/GL bit is not set in any data byte that has been transferred, latching does not occur.
⏵ SPI_100
Requirement removed.
⏵ SPI_21
When the Global/Local Latch (GLEN) bit in byte2 is set to 0 (local latching), and { PVER, PHOR } is not equal to 2b'00, then the Tx/Rx/GL (TRX/GL) bit in byte3 of the LCL_FBS or GBL_FBS command shall select if the operation mode will be RX (TRX = 0) or TX (TRX = 1).
⏵ SPI_106
When the Global/Local Latch (GLEN) bit in byte2 is set to 0 (local latching), and { PVER, PHOR } is equal to 2b'00, then the Tx/Rx/GL (TRX/GL) bit in byte4 of the LCL_FBS or GBL_FBS command shall select if the operation mode will be RX (TRX = 0) or TX (TRX = 1). The Tx/Rx/GL (TRX/GL) bit in byte3 shall be ignored (reserved).
⏵ SPI_70
When the Global/Local Latch (GLEN) bit in byte2 is set to 1 (global latching), and { PVER, PHOR } is not equal to 2b'00, then the Tx/Rx/GL (TRX/GL) bit in byte3 of the LCL_FBS or GBL_FBS command shall indicate if this was the last data byte that has been transferred (TRX/GL=1) or there are more data bytes expected to come (TRX/GL=0).
⏵ SPI_107
When the Global/Local Latch (GLEN) bit in byte2 is set to 1 (global latching), and { PVER, PHOR } is equal to 2b'00, then the Tx/Rx/GL (TRX/GL) bit in byte4 of the LCL_FBS or GBL_FBS command shall indicate if this was the last data byte that has been transferred (TRX/GL=1) or there are more data bytes expected to come (TRX/GL=0). The Tx/Rx/GL (TRX/GL) bit in byte3 shall be ignored (reserved).
⏵ SPI_71
The Tx/Rx (TRX) bit in byte2 of the LCL_FBS or GBL_FBS command shall select if the operation mode will be RX (TRX = 0) or TX (TRX = 1) when the Global/Local Latch (GL) bit in byte2 is set to 1 (global latching).
Otherwise, the bit shall be reserved.
⏵ SPI_22
When an LCL_FBS or GBL_FBS command is issued, and CTRL_CFG[0] (TRX_CONT_MODE) bit is set to 1 (SPI control),
then the SW_TRX[7] (TRX) bit shall be updated with the value of the
- Tx/Rx (TRX) bit provided in byte3 if GLEN is 0 and {PVER, PHOR} is not equal to 2b'00.
- Tx/Rx (TRX) bit provided in byte4 if GLEN is 0 and {PVER, PHOR} is equal to 2b'00.
- TRX bit in byte2 if GLEN is 1.
⏵ SPI_55
When an LCL_FBS or GBL_FBS command is issued, and CTRL_CFG[0] (TRX_CONT_MODE) bit is set to 0 (external pin configuration), then
the operation mode shall remain unchanged independently of the setting in the TRX/GL bit in byte3 (GLEN=0) or TRX bit in byte2 (GLEN=1).
Note: It shall be avoided that there is a conflict between the setting in the LCL_FBS or GBL_FBS command and the external TR pin.
⏵ SPI_95
The LUT Address given in byte3 or any following byte of the LCL_FBS or GBL_FBS command shall provide the 7-bit address of the LUT to access.
⏵ SPI_96
For Global Fast Beam Steering (GBL_FBS) command, Mode shall be set to 3'b111.
SPI - AC Specification
⏵ SPI_7
SPI clock (spi_clk) rate shall be up to 50MHz for read and up to 100MHz for write operation.
⏵ SPI_56
SPI clock (spi_clk) minimum pulse width high/low shall be 9ns for read and 4ns for write operation.
Note: Pulse width measured at 50% of the transition.
⏵ SPI_57
SPI input data (spi_mosi) to clock (spi_clk) rising edge setup time shall be at least 2ns.
⏵ SPI_58
SPI input data (spi_mosi) hold time shall be at least 4ns.
⏵ SPI_59
The input delay of the I/O buffer at pins SCLK, CSB and SPI_MOSI must not exceed 1ns.
⏵ SPI_60
The output delay of the I/O buffer at pin SPI_MISO must not exceed 1ns.
SPI - (Programmable) Chip Address
⏵ SPI_23
When spib_lvds is set to 0, F641X Digital shall support 5 address input signals (add_in[4:0]) for setting the chip address, whereas the lower 4 bits shall be derived from the external address pins (ADD[3:0]) and the MSB shall be tied LOW, resulting in add_in[4:0] = { 1'b0, ADD[3:0] }.
⏵ SPI_69
When spib_lvds is set to 1, addr_in[3:2] input signals shall be ignored and assumed to be low (set to 2'b00) for further processing (address comparison).
⏵ SPI_24
SPI shall have an internal, programmable 8-bit chip address stored in a shift register.
⏵ SPI_25
The selection of either the external or internal chip address shall be controlled by CTRL_CFG[11] (SHIFTREG_ADDR_EN). By default, the external chip address shall be selected.
⏵ SPI_26
The chip address shall be derived from the address input (addr_in[4:0]) pins when CTRL_CFG[11] is set to 1. Otherwise, it shall be derived from an 8-bit shift register.
⏵ SPI_27
The 8-bit shift register for the chip address shall be placed between address pin add_in[0] (input) and add_in_1_data (output).
⏵ SPI_28
Programming shall be initiated by setting CTRL_CFG[10] (SHIFTREG_ADDR_PROG) to 1.
⏵ SPI_33
Programming of the shift register shall be started by asserting spi_csb (driven low), followed by clock (spi_clk) and input data (spi_mosi) carrying the address bits.
⏵ SPI_29
Programming of the 8-bit shift register shall be terminated by deasserting spi_csb (driven high) after the last address bit was sent.
⏵ SPI_30
When programming is terminated, then CTRL_CFG[10] (SHIFTREG_ADDR_PROG) shall be cleared (set to 0) automatically, and CTRL_CFG[11] (SHIFTREG_ADDR_EN) shall be set to 1.
⏵ SPI_31
The 8-bit shift register shall only be reset by power-on (porb) or hardware (rstb) reset signal.
⏵ SPI_32
Programmable address bits shall be sent with MSB first.
⏵ SPI_76
For programming the SPI clock (spi_clk) rate shall be up to 50MHz.
⏵ SPI_34
Without releasing spi_csb an 8-bit data stream shall be sent to add_in[0] (MSB first). Data currently stored in the MSB of the 8-bit shift register shall be pushed out on add_in_1_data.
⏵ SPI_35
When programming is initiated, the add[1] I/O-buffer shall be configured to output mode by driving the add_in_1_oe high.
⏵ SPI_36
Writing 0 to CTRL_CFG[10] (SHIFTREG_ADDR_PROG) shall have no effect.
⏵ SPI_103
CTRL_CFG[11] (SHIFTREG_ADDR_EN) shall only be cleared (set to 0) by power-on (porb) or hardware (rstb) reset signal.
SPI - Cyclic Redundancy Check (CRC)
⏵ SPI_37
A Cyclic Redundancy Check (CRC) component shall be implemented as a linear feedback shift register (LFSR) to detect protocol and communication errors on the SPI interface.
⏵ SPI_38
It shall be possible to enable and disable the CRC by setting CTRL_CFG[7] (ERR_DET_EN) to 1 (enable) and 0 (disable) respectively. By default, the CRC shall be disabled.
⏵ SPI_39
The degree of the polynomial shall be 16.
⏵ SPI_40
The polynomial used in the CRC component shall be CRC-16-CCITT (0x8810, x^16 +x^12 +x^5 +1) with a seed value of 0xFFFF.
⏵ SPI_41
The polynomial shall be fixed and not programmable.
⏵ SPI_42
The CRC error detection feature shall be used for LCL_REG_WR and GLB_REG_WR commands.
⏵ SPI_43
The LFSR must be initialized (set to 0xFFFF) automatically before each write access.
⏵ SPI_44
When enabled, the CRC error detection feature shall extend a valid SPI frame by 16 SPI clock (spi_clk) cycles.
Note: These 16 extra cycles are needed to send two CRC bytes for that SPI frame.
⏵ SPI_45
The CRC componenet shall not augment a zero-length message with 16 zero bits.
Note: Referring to SPI_40 this implementation is known as CRC-16-CCITT-FALSE.
⏵ SPI_46
The CRC component shall be used to compute the CRC from a serial data stream of a maximum length (payload) of 280 bit.
Note: Refer to SPI_104 for specifying the exact number of data bytes that shall be transmitted when CRC is enabled. The minimum payload is calculated assuming 3 command and 1 data byte, and the maximum payload assumes 3 command and 32 data bytes. If more or less data bytes than specified in { NB1, NB0 } are transmitted in an SPI frame with CRC enabled, proper device operation is not guaranteed.
⏵ SPI_48
It shall not be possible to read out the computed CRC value on completion of the bitstream.
⏵ SPI_49
If the calculated CRC does not correspond to the transmitted CRC, the data shall not be discarded, but the CRC error flag (CTRL_CFG[8]) shall be asserted (set to 1).
⏵ SPI_50
Writing 1 to the CRC error flag (CTRL_CFG[8]) shall clear it. Writing 0 shall have no meaning.
REG - General Register Requirements
⏵ REG_1
The register map shall be according to the specification given in worksheet "Expanded Regs".
⏵ REG_2
The register bit fields shall be according to the description and specification given in worksheet "Register Definition".
⏵ REG_3
All registers having a "YES"-tag in column E (Buffered?) in worksheet "Expanded Regs" shall be considered bufferable.
REG - CTRL_CFG Register
⏵ REG_61
Through CTRL_CFG[9] (IO_PROTOCOL) the status of the spib_lvds input pin shall be read. This bit shall be read-only.
⏵ REG_68
Requirement removed.
⏵ REG_95
When CTRL_CFG[6] (TAL_RAL_EN) is set to 1, the functionality of the DAC Load bits (TAL and RAL) in byte3 of a LCL_REG_WR or GBL_REG_WR command wrt. the DAC mode (ON/OFF) setting shall be disabled. Otherwise, and by default, the functionality shall be enabled.
Note: Refer to DAC_2 for more information.
⏵ REG_4
A software reset event shall be initiated when CTRL_CFG[5] is set to 1. After reset, CTRL_CFG[5] shall be cleared (set to 0) automatically.
The functionality shall be the same as for a power-on reset event with the following exceptions:
- Scan and IO test mode shall not be disabled.
- SPI communication shall not be reset.
- The programmable chip address stored in the 8-bit shift register shall not be initialized to the default value.
Note: Refer to IO_39 for more information.
⏵ REG_14
When set to 1, CTRL_CFG[4] (IO_TEST) shall enable the IO test mode for IOs’ VIH/VIL test and MOSI’s VOL/VOH test. This bit shall be write-only and shall only be reset by a power-on reset. By default, IO test mode shall be disabled.
⏵ REG_7
When CTRL_CFG[3] (MANUAL_EN) is set to 1, it shall be possible to control the enable pin of individual channels by CH_ENS bits. This shall be the default value.
⏵ REG_18
When CTRL_CFG[2] (SCAN_MODE) is set to 1, scan test mode shall be enabled. This bit shall be write-only and shall only be reset by a power-on or hardware reset. By default, scan test mode shall be disabled.
⏵ REG_9
When CTRL_CFG[1] (SYNC_TRX) is set to 1, FEMs and internal SW shall be controlled by SW_TRX[7] (TRX) or tr input pin (dependent on CTRL_CFG[0]). Otherwise, they shall be controlled by TRX Switch Control (SW_TRX) register. By default, they shall be controlled by TRX Switch Control (SW_TRX) register
⏵ REG_11
When CTRL_CFG[0] is set to 1, SW_TRX[7] (TRX) shall control the operation mode (1=TX, 0=RX). By default, the operation mode shall be RX.
⏵ REG_12
When CTRL_CFG[0] is set to 0, SW_TRX[7] (TRX) shall be overwritten with the value of the tr input signal.
Note: This way, the state of the TR pin can be read back from this bit.
⏵ REG_13
When CTRL_CFG[0] is set to 0, the tr input signal shall control the operation mode (1=TX, 0=RX).
⏵ REG_70
By default, CTRL_CFG[0] shall be set to 1.
REG - CHIP_INFO Register
⏵ REG_15
CHIP_INFO[7:6] (OSC_FREQ[1:0]) shall select the oscillator frequency (0=80MHz, 1=40MHz, 2=20MHz, 3=OFF). By default, the oscillator frequency shall be 80MHz.
⏵ REG_16
When set to 1, CHIP_INFO[5] (OSC_EN) shall enable the oscillator. Otherwise, the oscillator shall be disabled. By default, it shall be disabled.
⏵ REG_17
When set to 1, CHIP_INFO[4] (OTP_FSM_START) shall start the OTP state machine to read all data from the OTP memory to the OTP_DATAn registers. This bit shall be write-only and shall be cleared automatically once the transfer of the OTP bits is completed.
⏵ REG_51
If not yet enabled already, writing 1 to CHIP_INFO[4] (OTP_FSM_START) shall enable the oscillator, and the status of CHIP_INFO[5] (OSC_EN) shall be updated accordingly.
⏵ REG_19
Requirement removed.
⏵ REG_20
Requirement removed.
⏵ REG_21
CHIP_INFO[3:0] (SA_INDEX[3:0]) shall store the sub-array index of the chip that is used for comparison by all global SPI commands. By default, CHIP_INFO[3:0] shall be set to 0x0.
REG - PIN_CFG Register
⏵ REG_22
PIN_CFG[6:2] shall select the mode that defines the role of the external pin TR, TLOAD and RLOAD according to worksheet 'External Pin Cfg'. By default, PIN_CFG[6:2] shall be set to 0x0.
⏵ REG_23
Requirement removed.
REG - H/VLUT_INFO/START/STOP Registers
⏵ REG_24
HLUT_INFO[14:8] shall store the current (active) LUT pointer (index) for horizontal TX SRAM. This bit field shall be read-only. By default, HLUT_INFO[14:8] shall be set to 0x0.
⏵ REG_25
HLUT_INFO[14:8] shall automatically be updated when a LCL_FBS or GBL_FBS SPI command is issued, the device is addressed and the horizontal LUT pointer (PHOR) is set to 1.
⏵ REG_26
HLUT_INFO[6:0] shall store the current (active) LUT pointer (index) for horizontal RX SRAM. This bit field shall be read-only. By default, HLUT_INFO[6:0] shall be set to 0x0.
⏵ REG_27
HLUT_INFO[6:0] shall automatically be updated when a LCL_FBS or GBL_FBS SPI command is issued, the device is addressed and the horizontal LUT pointer (PHOR) is set to 1.
⏵ REG_28
VLUT_INFO[14:8] shall store the current (active) LUT pointer (index) for vertical TX SRAM. This bit field shall be read-only. By default, VLUT_INFO[14:8] shall be set to 0x0.
⏵ REG_29
VLUT_INFO[14:8] shall automatically be updated when a LCL_FBS or GBL_FBS SPI command is issued, the device is addressed and the vertical LUT pointer (PVER) is set to 1.
⏵ REG_30
VLUT_INFO[6:0] shall store the current (active) LUT pointer (index) for vertical RX SRAM. This bit field shall be read-only. By default, VLUT_INFO[6:0] shall be set to 0x0.
⏵ REG_31
VLUT_INFO[6:0] shall be updated automatically when a LCL_FBS or GBL_FBS SPI command is issued, the device is addressed and the vertical LUT pointer (PVER) is set to 1.
⏵ REG_71
HLUT_START[14:8] shall store the start LUT pointer (index) for horizontal TX SRAM when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, HLUT_START[14:8] shall be set to 0x0.
⏵ REG_72
HLUT_START[6:0] shall store the start LUT pointer (index) for horizontal RX SRAM when when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, HLUT_START[6:0] shall be set to 0x0.
⏵ REG_73
HLUT_STOP[14:8] shall store the stop LUT pointer (index) for horizontal TX SRAM when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, HLUT_STOP14:8] shall be set to 127.
⏵ REG_74
HLUT_STOP[6:0] shall store the stop LUT pointer (index) for horizontal RX SRAM when when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, HLUT_STOP[6:0] shall be set to 127.
⏵ REG_75
VLUT_START[14:8] shall store the start LUT pointer (index) for vertical TX SRAM when when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, VLUT_START[14:8] shall be set to 0x0.
⏵ REG_76
VLUT_START[6:0] shall store the start LUT pointer (index) for vertical RX SRAM when when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, VLUT_START[6:0] shall be set to 0x0.
⏵ REG_77
VLUT_STOP[14:8] shall store the stop LUT pointer (index) for vertical TX SRAM when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, VLUT_STOP14:8] shall be set to 127.
⏵ REG_78
VLUT_STOP[6:0] shall store the stop LUT pointer (index) for vertical RX SRAM when when external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0). By default, VLUT_STOP[6:0] shall be set to 127.
⏵ REG_79
The HLUT_INFO and VLUT_INFO registers shall be overwritten with the values of HLUT_START and VLUT_START registers respectively when external pin configuration gets enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0).
⏵ REG_80
HLUT_INFO[14:8] shall automatically be incremented by one when
- the external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0), and
- SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled), and
- a "Latch next TX" or "TX+1" action is triggered on external pins.
When reaching HLUT_STOP[14:8], HLUT_INFO[14:8] shall be set to HLUT_START[14:8].
Note: Refer to IO_43 and IO_45 for more information.
⏵ REG_81
HLUT_INFO[6:0] shall automatically be incremented by one when
- the external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0), and
- SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled), and
- a "Latch next RX" or "RX+1" action is triggered on external pins.
When reaching HLUT_STOP[6:0], HLUT_INFO[6:0] shall be set to HLUT_START[6:0]."
Note: Refer to IO_44 and IO_46 for more information.
⏵ REG_82
VLUT_INFO[14:8] shall automatically be incremented by one when
- the external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0), and
- SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled), and
- a "Latch next TX" or "TX+1" action is triggered on external pins.
When reaching VLUT_STOP[14:8], VLUT_INFO[14:8] shall be set to VLUT_START[14:8]."
Note: Refer to IO_43 and IO_45 for more information.
⏵ REG_83
VLUT_INFO[6:0] shall automatically be incremented by one when
- the external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0), and
- SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled), and
- a "Latch next RX" or "RX+1" action is triggered on external pins.
When reaching VLUT_STOP[6:0], VLUT_INFO[6:0] shall be set to VLUT_START[6:0]."
Note: Refer to IO_44 and IO_46 for more information.
⏵ REG_69
H/VLUT_START/STOP registers shall only be applicable if the external pin configuration is enabled (CTRL_CFG[0] (TRX_CONT_MODE) is set to 0).
REG - BIST/CRC_RESULT Registers
⏵ REG_85
BIST[4:3] (SRAM_SEL[1:0]) shall select the look-up table (LUT) that is used for initialization, cyclic redundancy check (CRC) or embedded memory self-test (BIST).
Note: Refer to REG_86..88 for more information about triggering such actions.
⏵ REG_86
When set to 1, BIST[2] (SRAM_CRC) shall trigger a cyclic redundancy check (CRC) of the content of the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]). This bit shall not be cleared automatically, but must be set to 0 by system software.
Note: Refer to LUT_3..5 for more information.
⏵ REG_87
When set to 1, BIST[1] (SRAM_BIST) shall trigger the embedded memory self-test (BIST) of the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]). This bit shall not be cleared automatically, but must be set to 0 by system software.
Note: Refer to LUT_1..2 for more information.
⏵ REG_88
When set to 1, BIST[0] (SRAM_INIT) shall trigger the initialization of the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]), and set all bits to 0. This bit shall not be cleared automatically, but must be set to 0 by system software.
⏵ REG_89
When any of a cyclic redundancy check (CRC) or embedded memory self-test (BIST) or LUT (SRAM) initialization is completed, BIST[11] (SRAM_DONE) shall be set to 1 for the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]). If BIST[11] is already set to 1, the status shall remain unchanged.
⏵ REG_90
BIST[11] (SRAM_DONE) shall be cleared (set to 0) for the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]) if BIST[2:0] ({ SRAM_CRC, SRAM_BIST, SRAM_INIT }) is set to 3'b000.
⏵ REG_91
The number of errors that occured during an embedded memory self-test (BIST) shall be read in BIST[10:8] (SRAM_ERR[2:0]) for the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]) as follows:
0: No error.
4: One stuck-at '1' fault at an even or one stuck-at '0' fault at an odd bit location.
5: One stuck-at '1' fault at an odd or one stuck-at '0' fault at an even bit location.
7: More than one error occurred.
⏵ REG_92
The BIST error counter shall be cleared (set to 3'b000) for the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]) when BIST[1] (SRAM_BIST) is set to 0.
⏵ REG_93
The computed CRC value shall be shown in the SRAM CRC Result (CRC_RESULT) register for the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]).
⏵ REG_65
The default value of the CRC_RESULT register shall be 0xFFFF.
REG - SW_TRX Register
⏵ REG_5
When set to 1, SW_TRX[11] (MB_EN) shall enable the chip reference bias. Otherwise, it shall be disabled. By default, it shall be enabled.
⏵ REG_6
It shall be possible to read the SW_TRX[11] (MB_EN) value on MBIAS[0].
⏵ REG_8
When SW_TRX[10] (STANDBY) is set to 1, all receive and transmit channels and DACs shall be disabled. This shall be the default value.
⏵ REG_10
When set to 1, channels with horizontal (SW_TRX[9]) or vertical (SW_TRX[8]) polarization shall be enabled. Otherwise, they shall be disabled.
⏵ REG_32
When SW_TRX[4] (SW_DRV_EN_TR) is set to 1, dependent on SW_TRX[6] (SW_FEM_TR_MODE) either the positive (SW_TRX[6]=0) or negative (SW_TRX[6]=1) switch shall be enabled, and the drvenp and drvenn output signal driven high respectively. Otherwise (SW_TRX[4]=0), both the positive and negative switches shall be disabled (float). By default, all switches shall be disabled.
Note: Refer to equation TX_RX_CH_ENs__3 for more information.
⏵ REG_33
When external FEM switches are enabled, SW_TRX[5] (SW_DRV_TR_STATE) shall define the output level of the associated pins. In TX-mode, that shall be "GND" if SW_TRX[5]=0 and "High/Low" if SW_TRX[5]=1. In RX-mode, it shall be vice versa. By default, the output level shall be "GND".
Note: Refer to equation TX_RX_CH_ENs__3 for more information.
⏵ REG_34
Requirement removed.
⏵ REG_35
When CTRL_CFG[1] (SYNC_TRX) is set to 0, SW_TRX[3] (TRX_EXTH) shall select the operating mode (1=TX, 0=RX) of the external FEM SWs for horizontal polarization. By default, the SWs shall be set to RX.
Note: Refer to equation TX_RX_CH_ENs__3 for more information.
⏵ REG_36
When CTRL_CFG[1] (SYNC_TRX) is set to 0, SW_TRX[2] (TRX_EXTV) shall select the operating mode (1=TX, 0=RX) of the external FEM SWs for vertical polarization. By default, the SWs shall be set to RX.
Note: Refer to equation TX_RX_CH_ENs__3 for more information.
⏵ REG_37
When CTRL_CFG[1] (SYNC_TRX) is set to 0, SW_TRX[1] (TRX_BFH) shall select the operating mode (1=TX, 0=RX) of the BF SWs for horizontal polarization. By default, the SWs shall be set to RX.
Note: Refer to equation TX_RX_CH_ENs__2 for more information.
⏵ REG_38
When CTRL_CFG[1] (SYNC_TRX) is set to 0, SW_TRX[0] (TRX_BFV) shall select the operating mode (1=TX, 0=RX) of the BF SWs for vertical polarization. By default, the SWs shall be set to RX.
Note: Refer to equation TX_RX_CH_ENs__2 for more information.
REG - CH_ENS Register
⏵ REG_39
When CTRL_CFG[3] (MANUAL_EN) is set to 1, it shall be possible to enable (CH_ENS[i]=1, i=0..7) or disable (CH_ENS[i]=0, i=0..7) the associated transmit (txv1..4_en and txh1..4_en) output signals according to equation TX_RX_CH_ENs__1. By default, all TX channels shall be disabled.
⏵ REG_40
When CTRL_CFG[3] (MANUAL_EN) is set to 1, it shall be possible to enable (CH_ENS[i]=1, i=8..15) or disable (CH_ENS[i]=0, i=8..15) the associated receive (rxv1..4_en and rxh1..4_en) output signals according to equation TX_RX_CH_ENs__1. By default, all RX channels shall be disabled.
REG - ADC_CFG Register
⏵ REG_52
ADC_CFG[15:11] (ADC_SEL[4:0]) shall determine the ADC input source when ADC_CFG[10] is 1. The coding shall be as follows:
ADC Mux Selection Bits:
5'h1F: VSENS4
5'h1E: VSENS3
5'h1D: VSENS2
5'h1C: VSENS1
5'h1B: UNUSED
5'h1A: VNEG
5'h19: VDDPA
5'h18: DVDD
5'h17: VDD
5'h16: IDC
5'h15: TSENS2
5'h14: TSENS1
5'h13: PREF10
5'h12: PDET10
5'h11: PREF9
5'h10: PDET9
5'h0F: PREF8
5'h0E: PDET8
5'h0D: PREF7
5'h0C: PDET7
5'h0B: PREF6
5'h0A: PDET6
5'h09: PREF5
5'h08: PDET5
5'h07: PREF4
5'h06: PDET4
5'h05: PREF3
5'h04: PDET3
5'h03: PREF2
5'h02: PDET2
5'h01: PREF1
5'h00: PDET1
By default, PDET1 (ADC_CFG[15:11]=0x0) shall be selected.
⏵ REG_53
When ADC_CFG[10] (ADC_SEL_SOURCE) is set to 1, the input source of the ADC shall be selected by ADC_CFG[15:11] (ADC_SEL[4:0]). Otherwise, and by default, it shall be selected by the Sensor Activation 1 (ADC_SRQ1) register.
⏵ REG_54
ADC_CFG[9:7] (ADC_AVG[2:0]) shall determine the number (n) of data that are used for averaging as follows:
n = 1, for ADC_AVG[2:0]=0 (no averaging).
n = 2^ADC_AVG, for ADC_AVG[2:0]=1..6.
n = 64, for ADC_AVG[2:0]=7.
By default, there shall be 64 data used for averaging (ADC_AVG[2:0]=7).
⏵ REG_55
When ADC_CFG[6] (PD_DIFF_MODE) is set to 1, PDET data shall be stored as measured (after averaging, refer to REG_54). Otherwise, and by default, the difference PREF-PDET shall be stored.
⏵ REG_66
When ADC_CFG[6] (PD_DIFF_MODE) is set to 0, and the result of PREF-PDET is less than zero, 0x0 shall be stored.
REG - Sensor Registers
⏵ REG_56
When ADC_CFG[10] (ADC_SEL_SOURCE) is set to 0, writing 1 to any bit of the ADC_SRQ1 register shall trigger the whole sequence for the associated sensor measurement. It shall enable the oscillator, set the ADC channel, start of the ADC operation, and write the result to the associated ADC Data register. Writing 0 to any bit shall have no meaning.
⏵ REG_84
When ADC_CFG[10] (ADC_SEL_SOURCE) is set to 1, any write access to the ADC_SRQ1 register shall trigger the whole sequence for the selected sensor measurement.
Note: Refer to REG_52 for determining the ADC input source.
⏵ REG_57
When the oscillator gets enabled with the start of the ADC operation, the status of CHIP_INFO[5] (OSC_EN) shall be updated accordingly.
⏵ REG_58
ADC_SRQ1 shall determine the ADC input source when ADC_CFG[10] is 0. The assignment of bits shall be as follows:
[15]: TSENS2, reads TSENS2 (ADC_SEL 0x15) - refer to ADC_17 and ADC_6 for more information.
[14]: TSENS1, reads TSENS1 (ADC_SEL 0x14)- refer to ADC_16 and ADC_6 for more information.
[13]: VSENS_1_2, reads VSENS1 and VSENS2 external pins (ADC_SEL 0x1C, 0x1D).
[12]: VSENS_3_4 reads VSENS3 and VSENS4 external pins (ADC_SEL 0x1E, 0x1F).
[11]: VSENS_NEG, reads the -5V voltage supply (ADC_SEL 0x1A).
[10]: DC_SENS, reads VDD, DVDD, VDDPA and current sensors (ADC_SEL 0x16, 0x17, 0x18, 0x19).
[9]: PDET_RFC_H, reads PDET10 and PREF10 (ADC_SEL 0x12, 0x13) - refer to REG_55 for more information.
[8]: PDET_TX4_H, reads PDET9 and PREF9 (ADC_SEL 0x10, 0x11) - refer to REG_55 for more information.
[7]: PDET_TX3_H, reads PDET8 and PREF8 (ADC_SEL 0x0E, 0x0F) - refer to REG_55 for more information.
[6] PDET_TX2_H, reads PDET7 and PREF7 (ADC_SEL 0x0C, 0x0D) - refer to REG_55 for more information.
[5] PDET_TX1_H, reads PDET6 and PREF6 (ADC_SEL 0x0A, 0x0B) - refer to REG_55 for more information.
[4]: PDET_RFC_V, reads PDET5 and PREF5 (ADC_SEL 0x08, 0x09) - refer to REG_55 for more information.
[3]: PDET_TX4_V, reads PDET4 and PREF4 (ADC_SEL 0x06, 0x07) - refer to REG_55 for more information.
[2]: PDET_TX3_V, reads PDET3 and PREF3 (ADC_SEL 0x04, 0x05) - refer to REG_55 for more information.
[1]: PDET_TX2_V, reads PDET2 and PREF2 (ADC_SEL 0x02, 0x03) - refer to REG_55 for more information.
[0]: PDET_TX1_V, reads PDET1 and PREF1 (ADC_SEL 0x00, 0x01) - refer to REG_55 for more information.
By default, no source shall be selected.
⏵ REG_59
By default, the value of the SENSOR_EN register shall be 0x0 (no sensor enabled).
⏵ REG_60
When ADC_CFG[10] (ADC_SEL_SOURCE) is 0, writing 1 to any bit in the ADC_SRQ1 register shall also set the associated bit in the SENSOR_EN register.
⏵ REG_64
When ADC_CFG[10] (ADC_SEL_SOURCE) is 0, all bits in the SENSOR_EN register shall be cleared (set to 0) at the end of all ADC operations.
⏵ REG_62
SENSOR_CFG[13:12] (TSENS_POL_CFG[1:0]) shall select the setting that is used for temperature sensor measurements.
When set to 2'b00, two measurements, TSENS_POL0 and TSENS_POL1, shall be executed. In the first measurement d_tsens_pol shall be driven low, and in the second measurement it shall be driven high.
When set to 2'b01, two measurements, TSENS_POL0 and TSENS_POL1, shall be executed, and in both measurements d_tsens_pol shall be driven low.
When set to 2'b10, two measurements, TSENS_POL0 and TSENS_POL1, shall be executed, and in both measurements d_tsens_pol shall be driven high.
When set to 2'b11, the same procedure shall be executed as for 2'b00.
Note: TSENS_POL_CFG[1:0]=2'b11 shall not be used in the application. When set to 2'b11, no operation (NOP) could also be a possible solution.
⏵ REG_67
The setting of SENSOR_CFG[13:12] (TSENS_POL_CFG[1:0]) shall be applicable independently of the ADC_CFG[10] (ADC_SEL_SOURCE).
REG - SCRATCH Register
⏵ REG_50
In the SCRATCH register there shall be 2 bytes of memory for arbitrary data storage. This data shall not affect the operation of the device.
REG - TX/RX Registers
⏵ REG_63
As for the data in the TXVn/TXHn/RXVn/RXH_OFFSET (for n = 1; n <= 4) registers, the phase offset (TX/RX_PH_OFF) shall be stored in twos (2s) complement format, whereas channel bias (TX/RX_CH_BIAS) and align offset (TX/RX_ALIGN_OFF) shall be stored as absolute values.
⏵ REG_102
When a transfer of data to the TXVn/TXHn_SET (n=1..4) active registers is initiated, the value of the TXVn/TXHn_SET (n=1..4) output registers shall be generated according to the following equation:
TXVn_SET[9:0] (output) = TXVn_SET[9:0] (buffer)
TXHn_SET[9:0] (output) = TXHn_SET[9:0] (buffer)
TXVn_SET[15:10] (output) = TXVn_SET[15:10] (buffer) +/- TXVn_OFFSET[7:4]
TXHn_SET[15:10] (output) = TXHn_SET[15:10] (buffer) +/- TXHn_OFFSET[7:4]
Refer to SPI_8, IO_35, IO_41, and IO_43 for more information.
⏵ REG_103
When a transfer of data to the RXVn/RXHn_SET (n=1..4) active registers is initiated, the value of the RXVn/RXHn_SET (n=1..4) output registers shall be generated according to the following equation:
RXVn_SET[9:0] (output) = RXVn_SET[9:0] (buffer)
RXHn_SET[9:0] (output) = RXHn_SET[9:0] (buffer)
RXVn_SET[15:10] (output) = RXVn_SET[15:10] (buffer) +/- RXVn_OFFSET[7:4]
RXHn_SET[15:10] (output) = RXHn_SET[15:10] (buffer) +/- RXHn_OFFSET[7:4]
Refer to SPI_9, IO_42, and IO_44 for more information.
⏵ REG_94
[OPTIONAL] The host shall have the option to read from either the TXVn/TXHn/RXVn/RXHn_SET (n=1..4) buffer, active or output register when accessing the TXVn/TXHn/RXVn/RXHn_SET register. The TX/RX read back option shall be configured by the CTRL_CFG[14:13] (READBACK[1:0]) bits. By default, data from the TXVn/TXHn/RXVn/RXHn_SET (n=1..4) active registers shall be read.
REG - DAC Registers
⏵ REG_96
When DAC n (n=1..10) is enabled, the DAC_ONn register shall provide the DAC input value for ON-mode.
⏵ REG_97
When DAC n (n=1..10) is disabled, dependent on the setting in the PA_LNA_DAC_CFG1 register either the DAC_PA_OFF (PA_LNA_CONTROL[n-1]=1) or DAC_LNA_OFF (PA_LNA_CONTROL[n-1]=0) register shall provide the DAC input value for OFF-mode.
⏵ REG_98
The status (mode) of a DAC n (n=1..10) shall be read in the DAC_STATE[n-1] bit of the DAC_STATUS register. The bit shall be read as 1 if the DAC is enabled, and as 0 if it is disabled.
⏵ REG_99
DAC_STATUS[13:12] ({ TAL, RAL }) bits shall hold the status of the DAC Load bits set in byte3 of the last LCL_REG_WR or GBL_REG_WR command.
⏵ REG_100
DAC_STATUS[15:14] ({ TX_DAC_EN, RX_DAC_EN }) bits shall hold the enable status of all DACs configured as 'PA' (TX_DAC_EN) and 'LNA' (RX_DAC_EN) in the PA_LNA_DAC_CFG1 register respectively. The respective bit shall be read as 1 if the DACs are enabled (ON), and it is read as 0 if they are disabled (OFF).
⏵ REG_101
PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTROL[n-1]) (n=1..10) bits shall select if DAC n shall operate as PA (PA_LNA_DAC_CFG1[n-1]=1) or LNA (PA_LNA_DAC_CFG1[n-1]=0) DAC.
REG - OTP Registers
⏵ REG_41
There shall be no error detection when reading data from the OTP memory.
⏵ REG_42
The status of CHIP_INFO[4] (OTP_FSM_START) shall be mirrored in OTP_CFG[15] (OTP_FSM_START). OTP_CFG[15] shall be read-only.
⏵ REG_43
Requirement removed.
⏵ REG_44
Writing 1 to OTP_CFG[13] shall latch the data read from the OTP memory to the selected OTPn_DATA register.
⏵ REG_45
OTP_CFG[12:0] shall allow manual reading from the OTP memory or burn fuses when the oscillator clock is disabled or not running. By default, OTP_CFG[12:0] shall be set to 0x14.
⏵ REG_46
OTP_CFG[3:2] shall be used to test the robustness of the read operation. The following settings shall be applicable:
00: Reduced reference current.
01: Normal operation (default).
10: Enhanced reference current.
11: Extremely enhanced reference current (not in use).
⏵ REG_47
Requirement removed.
⏵ REG_48
Requirement removed.
⏵ REG_49
The default value of the OTPn_DATA register shall be 0x0.
TECH - Technology
⏵ TECH_1
F641X shall be developed based on Jazz Semiconductor SBC18HX process.
⏵ TECH_2
F641X Digital core voltage shall be 1.8V +/- 10%.
⏵ TECH_3
The junction temperature shall be at least -40degC and shall not exceed 125degC.
IO - General Signals
⏵ IO_1
The signals specified in worksheet "IOs_F641x" shall be implemented at the interface of F641X Digital.
⏵ IO_3
Requirement removed.
⏵ IO_21
A Power On Reset (POR) shall be initiated by a logic low on the porb input port. The POR shall reset all F641X Digital blocks.
⏵ IO_39
A hardware reset shall be initiated by a logic low on the rstb input port. The functionality shall be the same as for a power-on reset event.
Note: Refer to IO_21 for more information.
⏵ IO_9
It shall be possible to read the value of the chip_id[15:0] input signals through the CHIP_ID register.
⏵ IO_10
The value of MBIAS register shall be output on mbias[15:0] signals.
IO - External Pins
⏵ IO_7
When the stdby input pin is set to 1, all receive and transmit channels as well as all DACs shall be disabled.
⏵ IO_22
The functionality of tr, tload and rload ports shall be according to the specification in worksheet 'External Pin Cfg'.
⏵ IO_37
Requirement removed.
IO - DAC Signals
⏵ IO_20
The value of PA_LNA_DAC_CFG1[15:10] register bits shall be output on dac_buff_ctrl[5:0] signals.
⏵ IO_40
The value of PA_LNA_DAC_CFG2[15:0] register bits shall be output on dac_vh_ctrl[15:0] signals.
⏵ IO_11
The value of PA_LNA_DAC_CFG3[9:0] (PA_LNA_ENn, n=1..10) register bits shall be output on dac1..10_en signals, if Standby mode is disabled, meaning that neither SW_TRX[10] (STANDBY) is set to 1 nor the external stdby pin is driven high. Whereas, PA_LNA_DAC_CFG3[0] corresponds to dac1_en, PA_LNA_DAC_CFG3[1] to dac2_en, and so forth.
Note: Refer to DAC_1 for more information.
⏵ IO_30
The value of PA_LNA_DAC_CFG4[15:12] shall be output on dac_lna_res[3:0] signals.
⏵ IO_31
The value of PA_LNA_DAC_CFG4[11:8] shall be output on dac_pa_res[3:0] signals.
⏵ IO_32
The value of PA_LNA_DAC_CFG4[7:4] shall be output on dac_lna_ref[3:0] signals.
⏵ IO_33
The value of PA_LNA_DAC_CFG4[3:0] shall be output on dac_pa_ref[3:0] signals.
⏵ IO_12
The dacN_data[8:0] (N=1..10) output signals shall be generated according to equation DAC_BIAS_Ctrl__1.
⏵ IO_13
Requirement removed.
⏵ IO_38
The value of DAC_BIAS_CTRL register shall be output on dac_bias_ctrl[15:0] signals.
IO - Common TX/RX Settings Signals
⏵ IO_5
The value of the BF switch control (trx_bfv_en, trx_bfv_en) output signals shall be set according to equation TX_RX_CH_ENs__2.
⏵ IO_6
The value of the SWCxy (x=H,V; y=P,N) control output signals (swchn, swchp, swcvn, swcvp, drvenn, drvenp) shall be set according to equation TX_RX_CH_ENs__3.
⏵ IO_28
The values of TXCOM_BIAS2[15:0], TXCOM_BIAS1[15:0], TXCOM_CFG[15:0], and TXCOM_TUNE[15:0] shall be output on tx_com[63:0] as follows:
tx_com[63:48]=TXCOM_BIAS2[15:0]
tx_com[47:32]=TXCOM_BIAS1[15:0]
tx_com[31:16]=TXCOM_CFG[15:0]
tx_com[15:0]=TXCOM_TUNE[15:0]
⏵ IO_29
The values of RXCOM_BIAS2[15:0], RXCOM_BIAS1[15:0], RXCOM_CFG[15:0], and RXCOM_TUNE[15:0] shall be output on rx_com[63:0] as follows:
rx_com[63:48]=RXCOM_BIAS2[15:0]
rx_com[47:32]=RXCOM_BIAS1[15:0]
rx_com[31:16]=RXCOM_CFG[15:0]
rx_com[15:0]=RXCOM_TUNE[15:0]
IO - TX/RX Channel Signals
⏵ IO_4
The value of the receive (rxv1..4_en and rxh1..4_en) and transmit (txv1..4_en and txh1..4_en) output signals shall be set according to equation TX_RX_CH_ENs__1.
⏵ IO_14
The value of TXVn/TXHn_SET output registers shall be output on txvN/txhN_set[15:0] signals, whereas n=N=1..4.
Note: Refer to REG_102 for more information.
⏵ IO_26
The value of RXVn/RXHn_SET output registers shall be output on rxvN/rxhN_set[15:0] signals, whereas n=N=1..4.
Note: Refer to REG_103 for more information.
⏵ IO_35
If the result of TXVn_SET[15:10] (buffer) +/- TXVn_OFFSET[7:4] is greater than 64, the overflow shall be ignored (in decimal it would be TXVn_SET[15:10] (buffer) + TXVn_OFFSET[7:4] - 64).
The same method shall be applied if the result of TXHn_SET[15:10] (buffer) + TXHn_OFFSET[7:4], RXVn_SET[15:10] (buffer) + RXVn_OFFSET[7:4] or RXHn_SET[15:10] (buffer) + RXHn_OFFSET[7:4]is greater than 64.
Note: Refer to REG_102 and REG_103 for more information.
⏵ IO_36
If the result of TXVn_SET[15:10] (buffer) - TXVn_OFFSET[7:4] is less than 0, than d'64 shall be added (in decimal it would be TXVn_SET[15:10] (buffer) - TXVn_OFFSET[7:4] + 64).
The same method shall be applied if the result of TXHn_SET[15:10] (buffer) - TXHn_OFFSET[7:4], RXVn_SET[15:10] (buffer) + RXVn_OFFSET[7:4] or RXHn_SET[15:10] (buffer) + RXHn_OFFSET[7:4] is less than 0.
Note: Refer to REG_102 and REG_103 for more information.
⏵ IO_34
The value of TXVn_OFFSET[3:0] shall be output on txvn_off[3:0] signals, the value of TXHn_OFFSET[3:0] on txhn_off[3:0], the value of RXVn_OFFSET[3:0] on rxvn_off[3:0], and the value of RXHn_OFFSET[3:0] on rxhn_off[3:0], whereas n=N=1..4.
⏵ IO_15
The value of TXVn_OFFSET[11:8] shall be output on txvN_bias[3:0] signals, the value of TXHn_OFFSET[11:8] on txhN_bias[3:0] signals, the value of RXVn_OFFSET[11:8] on rxvn_bias[3:0], the value of RXHn_OFFSET[11:8] on rxhn_bias[3:0], whereas n=N=1..4.
⏵ IO_27
The value of TXVn_OFFSET[15:11] shall be output on txvN_spare[4:0] signals, the value of TXHn_OFFSET[15:11] on txhN_spare[4:0] signals, the value of RXVn_OFFSET[15:11] on rxvN_spare[4:0], and the value of RXHn_OFFSET[15:11] on rxhN_spare[4:0], whereas n=N=1..4.
⏵ IO_19
Requirement removed.
⏵ IO_41
When external pin configuration is enabled (CTRL_CFG[0]=0), and either
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x6 or 0x9, and there is a transition on tload from 0 to 1 (rising edge), or
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x3 or 0xC, and tr is set to 1, and there is a transition on rload from 0 to 1 (rising edge).
then data of the
- TXVn Set (TXVn_SET, n = 1..4) buffer registers shall be transferred to the TXVn_SET active registers if SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled).
- TXHn Set (TXHn_SET, n = 1..4) buffer registers shall be transferred to the TXHn_SET active registers if SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled).
⏵ IO_42
When external pin configuration is enabled (CTRL_CFG[0]=0), and either
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x6 or 0x9, and there is a transition on rload from 0 to 1 (rising edge), or
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x3 or 0xC, and tr is set to 0, and there is a transition on tload from 0 to 1 (rising edge).
then data of the
- RXVn Set (RXVn_SET, n = 1..4) buffer registers shall be transferred to the RXVn_SET active registers if SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled).
- RXHn Set (RXHn_SET, n = 1..4) buffer registers shall be transferred to the RXHn_SET active registers if SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled).
⏵ IO_43
When external pin configuration is enabled (CTRL_CFG[0]=0), and
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x4 or 0x5 or 0x7 or 0x8, and there is a transition on tload from 0 to 1 (rising edge), or
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x1 or 0x2 or 0xA or 0xB, and tr is set to 1, and there is a transition on rload from 0 to 1 (rising edge).
then
- the active TXVn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to TXVn Set (TXVn_SET, n = 1..4) buffer and active registers if SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled).
- the active TXHn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to TXHn Set (TXHn_SET, n = 1..4) buffer and active registers if SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled).
⏵ IO_44
When external pin configuration is enabled (CTRL_CFG[0]=0), and
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x4 or 0x5 or 0x7 or 0x8, and there is a transition on rload from 0 to 1 (rising edge), or
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x1 or 0x2 or 0xA or 0xB, and tr is set to 0, and there is a transition on tload from 0 to 1 (rising edge).
then
- the active RXVn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to RXVn Set (RXVn_SET, n = 1..4) buffer and active registers if SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled).
- the active RXHn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to RXHn Set (RXHn_SET, n = 1..4) buffer and active registers if SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled).
⏵ IO_45
When external pin configuration is enabled (CTRL_CFG[0]=0), and
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x5 or 0x8, and there is a transition on rload from 0 to 1 (rising edge), or
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x2 or 0xB, and tr is set to 0, and there is a transition on tload from 0 to 1 (rising edge).
then
- the active TXVn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to TXVn Set (TXVn_SET, n = 1..4) buffer registers if SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled).
- the active TXHn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to TXHn Set (TXHn_SET, n = 1..4) buffer registers if SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled).
⏵ IO_46
When external pin configuration is enabled (CTRL_CFG[0]=0), and
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x5 or 0x8, and there is a transition on tload from 0 to 1 (rising edge), or
- PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x2 or 0xB, and tr is set to 1, and there is a transition on rload from 0 to 1 (rising edge).
then
- the active RXVn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to RXVn Set (RXVn_SET, n = 1..4) buffer registers if SW_TRX[8] (V_POL_EN) is set to 1 (channels with vertical polarization are enabled).
- the active RXHn LUT index shall be increased by 1 and data stored at this pointer shall be transferred to RXHn Set (RXHn_SET, n = 1..4) buffer registers if SW_TRX[9] (H_POL_EN) is set to 1 (channels with horizontal polarization are enabled).
IO - Oscillator Signals
⏵ IO_2
The oscillator clock (osc_clk) frequency may vary between 20MHz and 80MHz.
⏵ IO_8
The value of CHIP_INFO[7:6] shall be output on osc_freq[1:0] signals.
IO - ADC Signals
⏵ IO_16
The value of ADC_CFG[5:0] shall be output on { adc_aout_sel[1:0], adc_aout_en, adc_lsb_sel, adc_chopper_en, adc_i_2x } signals.
By default, ADC_CFG[5:0] shall be set to 0x0, that ADC_MUX is output on AOUT, AOUT mux is disabled, LSB is Vref/1023, chopper is disabled, and normal ADC bias current.
IO - Sensor Signals
⏵ IO_17
The value of SENSOR_EN[15:0] shall be output on sensor_en[15:0] signals.
⏵ IO_18
The value of SENSOR_CFG[15:0] shall be output on sensor_cfg[15:0] signals.
⏵ IO_23
The sensor bias enable (sensor_bias_en) output signal shall be driven high when any of SENSOR_EN[9:0] are 1.
IO - PCM Control Signals
⏵ IO_24
All signals associated to PCM (pcm_*) shall not be used, and therefore output signals shall be tied low and input signals left unconnected.
IO - Spare Signals
⏵ IO_25
The value of the Spare Register for Channels (TX_RX_SPARE) shall be output on spare[15:0] signals.
IO - AC Specification
⏵ IO_47
The input to output delay from tr/stdby to txv1..4_en/txh1..4_en/rxv1..4_en/rxh1..4_en/trx_bfv/trx_bfh/drvenn/drvenp/swchn/swchp/swcvn/swcvp must not exceed 20ns.
⏵ IO_48
tr/stdby/tload/rload pulse width (high and low) must be at least 125ns.
OSC - Oscillator Operation
⏵ OSC_1
The oscillator shall be enabled when either
- CHIP_INFO[5] (OSC_EN) is set to 1, or
- a write access to ADC_SRQ1 register is issued, or
- CHIP_INFO[4] (OTP_FSM_START) is set to 1.
ADC - ADC Operation
⏵ ADC_1
The ADC shall be enabled (adc_en signal driven high), when the ADC operation has been triggered (refer to REG_56).
Note: Refer to ADC_4 and ADC_5 for the delay between triggering the ADC operation and enabling the ADC.
⏵ ADC_2
The ADC base clock (base_clk) shall be derived from the oscillator clock (osc_clk) and dependent on the setting of CLK_CFG[11:8] as follows: base_clk = osc_clk / (CLK_CFG[11:8] + 1).
⏵ ADC_3
The ADC clock (adc_clk) shall be derived from the ADC base clock (base_clk) and dependent on the setting of CLK_CFG[7:0] as follows:
- Thigh(adc_clk) = T(base_clk) * (CLK_CFG[7:4] + 1)
- Tlow(adc_clk) = T(base_clk) * (CLK_CFG[3:0] + 1)
⏵ ADC_4
There shall be a programmable delay in multiples of ADC clock (adc_clk) cycles between the time the ADC is enabled and acquisition start as follows: Tdelay = T(adc_clk) * CLK_CFG[15:11].
⏵ ADC_5
63 osc_clk cycles after the ADC operation has been started, the ADC clock (adc_clk) shall be generated based on the CLK_CFG settings.
⏵ ADC_11
The ADC sampling (adc_sp) output signal shall be driven high for three (3) ADC clock (adc_clk) cycles after the ADC operation has been started. Otherwise, adc_sp shall be driven low.
Note: If the oscillator clock (osc_clk) and hence the ADC clock (adc_clk) are not running when the ADC operation has been started, an additional wait time as specified in ADC_5 has to be considered.
⏵ ADC_12
A 10-bit successive-approximation register (SAR) shall be used to supply an approximate digital code (adc_dac_in[9:0]) of Vdac to the ADC-internal DAC.
⏵ ADC_13
The initial value of the SAR shall be first set to midscale (that is, 10'b1000000000, where the MSB is set to 1).
⏵ ADC_14
If Vin is greater than Vdac, the comparator output (adc_1_bit) signal is driven high, and the MSB of the successive-approximation register shall remain at 1. Conversely, if Vin is less than Vdac, the comparator output is driven low and the MSB of the register shall be cleared to 0.
⏵ ADC_15
The SAR control logic shall then move to the next bit down, force that bit high, and do another comparison. The sequence shall continue all the way down to the LSB.
⏵ ADC_16
If TSENS1 is enabled - refer to REG_52 for more information - two measurements, TSENS_POL0 and TSENS_POL1, shall be executed and the result shall be caculated as follows:
TSENS1 = 0.5 * (TSENS_POL0 + TSENS_POL1)
Note: Refer to REG_62 for the value of d_tsens_pol that shall be used for the first (POL0) and second (POL1) measurement.
⏵ ADC_17
If TSENS2 is enabled - refer to REG_52 for more information - two measurements, TSENS_POL0 and TSENS_POL1, shall be executed and the result shall be caculated as follows:
TSENS2 = TSENS_POL1 - TSENS_POL0
If the result of TSENS_POL1 - TSENS_POL0 is less than zero, 0x0 shall be stored.
Note: Refer to REG_62 for the value of d_tsens_pol that shall be used for the first (TSENS_POL0) and second (TSENS_POL1) measurement.
⏵ ADC_6
When averaging is enabled (ADC_CFG[9:7]>0), then the converted data shall be added and divided (right-shifted) by the number of iterations.
Averaging for TSENS1, TSENS2 and PDETn (when ADC_CFG[6] (PD_DIFF_MODE) is set to 0, n=1..10), shall be done on the inner loop. For example, TSENS1(avg)=0.5*(SUM(TSENS_POL0)+SUM(TSENS_POL1))/n.
Note: The number (n) of iterations is specified in REG_54.
⏵ ADC_7
The resulting data shall be stored in the associated ADC_DATA_CHn (n=1..32) register, whereas n shall correspond to the channel selected in ADC_CFG[15:11]+1.
Note: For example, the data for TSENS1 (ADC_CFG[15:11]=0x14) shall be stored in ADC_DATA_CH21.
⏵ ADC_8
When conversion and averaging (if enabled) of all selected sources are completed, the ADC_DATA_CHn[10] (DONE) bits shall be set to 1, whereas n=ADC_CFG[15:11]+1.
⏵ ADC_9
ADC operation shall be done for all selected input sources (refer to REG_53 and REG_58) in a loop from 0 to 15.
⏵ ADC_18
Once the ADC operation of all selected channels is completed, the ADC shall be disabled (adc_en signal driven low).
⏵ ADC_10
When ADC_CFG[10] (ADC_SEL_SOURCE) is 0,
- the SENSOR_EN register shall be reset to 0x0 (all sensors disabled)
- CHIP_INFO[5] (OSC_EN) shall be cleared (set to 0, oscillator disabled)
once the ADC operation of all selected channels is completed.
LUT - Look-up Tables
⏵ LUT_1
There shall be an embedded memory self-test (BIST) for all look-up tables (LUTs) of the design.
Note: Refer to REG_87 for triggering the BIST.
⏵ LUT_2
The BIST shall use the following test algorithm:
- w(5), up addressing order
- r(5)-w(a)-r(a), up addressing order
- r(a)-w(5)-r(5), up addressing order
- r(5)-w(a)-r(a), down addressing order
- r(a)-w(5)-r(5), down addressing order
- r(5), down addressing order
Whereas,
w(5): writing 0x5555_5555_5555_5555 into an address location.
r(5): reading 0x5555_5555_5555_5555 from an address location.
w(a): writing 0xAAAA_AAAA_AAAA_AAAA into an address location.
r(a): reading 0xAAAA_AAAA_AAAA_AAAA from an address location.
up addressing order: address sequence is in ascending order from 0 to 2^7-1.
down addressing order: address sequence is in descending order from 2^7-1 to 0.
⏵ LUT_3
A Cyclic Redundancy Check (CRC) component shall be implemented as a linear feedback shift register (LFSR) to bit errors in the look-up tables (LUTs).
⏵ LUT_4
The degree of polynomial used in the CRC component shall be 16, and in particular CRC-16-CCITT (0x8810, x^16 +x^12 +x^5 +1) with a seed value of 0xFFFF shall be used. The polynomial shall be fixed and not programmable.
⏵ LUT_5
The LFSR must be initialized (set to 0xFFFF) automatically before each CRC.
⏵ LUT_6
The CRC componenet shall not augment a zero-length message with 16 zero bits.
Note: Referring to LUT_4 this implementation is known as CRC-16-CCITT-FALSE.
DAC - DAC Operation
⏵ DAC_1
DAC n (n=1..10) shall be disabled if one of the following conditions occur:
- Standby mode is enabled, meaning that either SW_TRX[10] (STANDBY) is set to 1 or the external stdby pin is driven high.
- the PA_LNA_ENn bit in the PA_LNA_DAC_CFG3 register is set to 0.
Note: Refer to IO_11 for more information.
⏵ DAC_2
If DAC n (n=1..10) is not disabled by any condition listed in DAC_1, it shall be enabled if any of the following conditions is met:
- When CTRL_CFG[0] (TRX_CONT_MODE) is set to 1 (SPI control), and
* SW_TRX[7] (TRX) and PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTRL[n-1]) are set to 1, and
+ CTRL_CFG[6] (TAL_RAL_EN) is set to 0, or
+ CTRL_CFG[6] (TAL_RAL_EN) is set to 1 and the TX DAC Load (TAL) bit in byte3 of a LCL_REG_WR or GBL_REG_WR command is set to 1.
* SW_TRX[7] (TRX) and PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTRL[n-1]) are set to 0 and
+ CTRL_CFG[6] (TAL_RAL_EN) is set to 0, or
+ CTRL_CFG[6] (TAL_RAL_EN) is set to 1 and the RX DAC Load (RAL) bit in byte3 of a LCL_REG_WR or GBL_REG_WR command is set to 1.
- When CTRL_CFG[0] (TRX_CONT_MODE) is set to 0 (external pin control), and
* PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to either 0x1 or 0x2 or 0x3, and
+ tr and tload and PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTRL[n-1]) are set to 1, or
+ tr and and PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTRL[n-1]) are set to 0, and rload is set to 1.
* PIN_CFG[6:2] (EXT_PIN_MODE[4:0]) is set to a value between 0x7 up to and including 0xC, and
+ tr and PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTRL[n-1]) are set to 1, or
+ tr and PA_LNA_DAC_CFG1[n-1] (PA_LNA_CONTRL[n-1]) are set to 0.
DFT - Scan Test
⏵ DFT_1
Scan Test mode shall be enabled by setting CTRL_CFG[2] (SCAN_MODE) to 1.
⏵ DFT_2
In Scan Test mode controllability features shall be added on inputs that don’t go directly to FFs.
⏵ DFT_3
During Scan Test all output signals to Analog Subsystem shall be forced to benign state according to column G in worksheet 'IOs_F641x'.
⏵ DFT_4
Observability FFs shall be added to all output signals that don’t come directly from a FF.
⏵ DFT_5
The (target) stuck-at fault coverage shall be 98.0%.
⏵ DFT_6
All Scan clocks shall be switched off in normal mode (root clock gating).
⏵ DFT_7
The frequency in shift mode shall be 20MHz.
⏵ DFT_8
In Scan Test mode all pull-up/down resistors (if any) shall be switched off.
⏵ DFT_9
Exclude FFs from the scan chain that must remain unchanged during Scan Test shall be:
- CTRL_CFG[2] (SCAN_MODE) register bit.
⏵ DFT_10
External pins of F641X Digital shall be shared in Scan Test mode as follows:
- spi_csb is an input pin and works as low active scan reset.
- add_in[2] is an input pin and works as high active scan enable.
- spi_clk is an input pin and works as scan clock.
- spi_mosi_in is an input pin and works as scan data 0 in.
- spi_miso_out is an output pin and works as scan data 0 out.
- add_in[0] is an input pin and works as scan data 1 in.
- add_in[1] is an output pin and works as scan data 1 out.
Note: Refer to DFT_1 and REG_18 for more information.
⏵ DFT_11
In Scan Test mode, there shall be no access to the SPI Interface.
⏵ DFT_12
To exit Scan Test mode, a power-on or hardware reset event shall be initiated by a minimum 20ns logic low on the porb and rstb pin respectively.
DFT - IO Test
⏵ DFT_13
IO Test structures shall be inserted into the F641X Digital for spi_csb, spi_clk, spi_mosi_in, spi_mosi_out, add_in[3:0], tr, tload, rload and stdby.
⏵ DFT_14
The test structures shall be used for testing and characterizing the following features:
- General input and output functional operation.
- Input and output voltage levels.
- Input leakage current.
⏵ DFT_15
rstb shall be excluded from IO Test because any input low value will issue a power-on reset.
⏵ DFT_16
IO Test shall be enabled by setting CTRL_CFG[4] (IO_TEST) to 1.
Note: Refer to REG_14 for more information.
⏵ DFT_17
In IO Test mode there shall be no access to the SPI Interface.
⏵ DFT_18
To exit IO Test mode, a power-on or hardware reset event shall be initiated by a minimum 20ns logic low on the porb and rstb pin respectively.