Interface/Signal Descriptions

Overview

This section provides information about the interfaces and signals of the Renesas f641x_dig.

In addition to describing the function of each signal, the signal descriptions in this section include the following information:

Active State: Indicates whether the signal is active high or active low. When a signal is not intended to be used in a particular application, then this signal needs to be tied or driven to the inactive state (opposite of the active state).

Synchronous To: Indicates which clock(s) in the subsystem sample this input (drive for an output). This clock might not be the same as the clock that other subsystem logic should use to clock (sample/drive) this pin.

Attributes used with 'Synchronous To':

� Clock name - The name of the clock that samples an input or drives an output.

� None - This attribute may be used for clock inputs, hard-coded outputs, feed-through (direct or combinatorial), dangling inputs, unused inputs and asynchronous outputs.

� Asynchronous - This attribute is used for asynchronous inputs and asynchronous resets.

The signals are grouped as follows:

� Reset Signals

� SPI Interface

� External Control Signals

� TX/RX Digital Output Signals

� Common TX/RX settings

� DAC Digital Output Signals

� Chip ID and Master Bias Control Signals

� TX/RX Channel Setting Signals

� Oscillator Signals

� ADC Interface

� Sensor Interface

� PCM Interface

� OTP Interface

� Spare Signals

Ports

The following table summarizes the signals of the Renesas f641x_dig.

Table: Renesas f641x_dig signal description.

Port Name	Type	Description
Reset Signals
porb	I	Low active power-on reset: 0=reset, 1=no reset. Active State: Low Synchronous To: Asynchronous
rstb	I	External RSTB pin. Active State: Low Synchronous To: Asynchronous
SPI Interface
spi_clk	I	SPI clock from master. Active State: N/A Synchronous To: None
spi_csb	I	SPI chip selection (low active): 0=chip selection, 1=no chip selection. Active State: Low Synchronous To: spi_clk
spi_mosi_in	I	SPI input data. Active State: N/A Synchronous To: spi_clk
spi_miso_out	O	SPI output data. Active State: N/A Synchronous To: spi_clk
spi_miso_oe	O	SPI output enable: 0=disable, 1=enable. Active State: High Synchronous To: spi_clk
add_in[4:0]	I	External, pin-configurable (hard-wired) address input. Active State: N/A Synchronous To: Asynchronous
add_in_1_data	O	Address output when configured in shift register programming mode. Connected to the output port of the add[1] I/O-buffer. Active State: N/A Synchronous To: spi_clk
add_in_1_oe	O	Address output enable when configured in shift register programming mode. Connected to the output enable port of the add[1] I/O buffer. Active State: High Synchronous To: spi_clk
External Control Signals
tr	I	External pin for TRX selection: 1=TX, 0=RX. Active State: N/A Synchronous To: Asynchronous
tload	I	External TX latch pin. Active State: High Synchronous To: Asynchronous
rload	I	External RX latch pin. Active State: High Synchronous To: Asynchronous
stdby	I	External STDBY pin. When set to 1, puts the chip in Standby mode (all ENs off). Active State: High Synchronous To: Asynchronous
spib_lvds	I	Input pin for SPI vs LVDS selection: 0=default single-ended SPI, 1=LVDS. Active State: N/A Synchronous To: Asynchronous
TX/RX Digital Output Signals
swchn	O	When set to 0, SWCHN (horizontal polarization, negative pins) output is -5V. When set to 1, output is 1.8V. Active State: N/A Synchronous To: Asynchronous
swchp	O	When set to 0, SWCHP (horizontal polarization, positive pins) output is 0V. When set to 1, output is 2.5V. Active State: N/A Synchronous To: Asynchronous
swcvn	O	When set to 0, SWCVN (vertical polarization, negative pins) output is -5V. When set to 1, output is 1.8V. Active State: N/A Synchronous To: Asynchronous
swcvp	O	When set to 0, SWCVP (vertical polarization, positive pins) output is 0V. When set to 1, output is 2.5V. Active State: N/A Synchronous To: Asynchronous
drvenn	O	When set to 0, SWCHN and SWCVN (horizontal and vertical polarization, negative pins) output are floating. Active State: High Synchronous To: Asynchronous
drvenp	O	When set to 0, SWCHP and SWCVP (horizontal and vertical polarization, positive pins) output are floating. Active State: High Synchronous To: Asynchronous
trx_bfh	O	BF switch control (horizontal polarization): 0=RX, 1=TX. Active State: N/A Synchronous To: Asynchronous
trx_bfv	O	BF switch control (vertical polarization): 0=RX, 1=TX. Active State: N/A Synchronous To: Asynchronous
rxh4_en	O	Receive channel 4 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxh3_en	O	Receive channel 3 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxh2_en	O	Receive channel 2 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxh1_en	O	Receive channel 1 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxv4_en	O	Receive channel 4 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxv3_en	O	Receive channel 3 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxv2_en	O	Receive channel 2 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
rxv1_en	O	Receive channel 1 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txh4_en	O	Transmit channel 4 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txh3_en	O	Transmit channel 3 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txh2_en	O	Transmit channel 2 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txh1_en	O	Transmit channel 1 enable (horizontal polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txv4_en	O	Transmit channel 4 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txv3_en	O	Transmit channel 3 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txv2_en	O	Transmit channel 2 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
txv1_en	O	Transmit channel 1 enable (vertical polarization): disable=0, enable=1. Active State: High Synchronous To: Asynchronous
Common TX/RX settings
tx_com[63:0]	O	Common TX settings: [63:48]=TXCOM_BIAS2, [47:32]=TXCOM_BIAS1, [31:16]=TXCOM_CFG, [15:0]=TXCOM_TUNE. Active State: N/A Synchronous To: spi_clk
rx_com[63:0]	O	Common RX settings: [63:48]=RXCOM_BIAS2, [47:32]=RXCOM_BIAS1, [31:16]=RXCOM_CFG, [15:0]=RXCOM_TUNE. Active State: N/A Synchronous To: spi_clk
DAC Digital Output Signals
dac_buff_ctrl[5:0]	O	PA_LNA_DAC_CFG1[15:10]. Active State: N/A Synchronous To: spi_clk
dac10_en	O	DAC @ register 0x6A enable. PA_LNA_DAC_CFG2[9] Active State: High Synchronous To: spi_clk
dac9_en	O	DAC @ register 0x69 enable. PA_LNA_DAC_CFG2[8] Active State: High Synchronous To: spi_clk
dac8_en	O	DAC @ register 0x68 enable. PA_LNA_DAC_CFG2[7] Active State: High Synchronous To: spi_clk
dac7_en	O	DAC @ register 0x67 enable. PA_LNA_DAC_CFG2[6] Active State: High Synchronous To: spi_clk
dac6_en	O	DAC @ register 0x66 enable. PA_LNA_DAC_CFG2[5] Active State: High Synchronous To: spi_clk
dac5_en	O	DAC @ register 0x65 enable. PA_LNA_DAC_CFG2[4] Active State: High Synchronous To: spi_clk
dac4_en	O	DAC @ register 0x64 enable. PA_LNA_DAC_CFG2[3] Active State: High Synchronous To: spi_clk
dac3_en	O	DAC @ register 0x63 enable. PA_LNA_DAC_CFG2[2] Active State: High Synchronous To: spi_clk
dac2_en	O	DAC @ register 0x62 enable. PA_LNA_DAC_CFG2[1] Active State: High Synchronous To: spi_clk
dac1_en	O	DAC @ register 0x61 enable. PA_LNA_DAC_CFG2[0] Active State: High Synchronous To: spi_clk
dac_lna_res[3:0]	O	Resolution control for LNA DACs. PA_LNA_DAC_CFG3[15:12] Active State: N/A Synchronous To: spi_clk
dac_pa_res[3:0]	O	Resolution control for PA DACs. PA_LNA_DAC_CFG3[11:8] Active State: N/A Synchronous To: spi_clk
dac_lna_ref[3:0]	O	Reference setting for LNA DACs. PA_LNA_DAC_CFG3[7:4] Active State: N/A Synchronous To: spi_clk
dac_pa_ref[3:0]	O	Reference setting for PA DACs. PA_LNA_DAC_CFG3[3:0] Active State: N/A Synchronous To: spi_clk
dac10_data[8:0]	O	DAC @ register 0x6A ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac9_data[8:0]	O	DAC @ register 0x69 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac8_data[8:0]	O	DAC @ register 0x68 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac7_data[8:0]	O	DAC @ register 0x67 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac6_data[8:0]	O	DAC @ register 0x66 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac5_data[8:0]	O	DAC @ register 0x65 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac4_data[8:0]	O	DAC @ register 0x64 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac3_data[8:0]	O	DAC @ register 0x63 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac2_data[8:0]	O	DAC @ register 0x62 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac1_data[8:0]	O	DAC @ register 0x61 ON and OFF value. Active State: N/A Synchronous To: spi_clk
dac_bias_ctrl[15:0]	O	DAC bias control enable. Active State: High Synchronous To: spi_clk
dac_vh_ctrl[15:0]	O	PA_LNA_DAC_CFG2[15:0] Active State: N/A Synchronous To: spi_clk
Chip ID and Master Bias Control Signals
chip_id[15:0]	I	According to CHIP_ID register bits. Active State: N/A Synchronous To: Asynchronous
mbias[15:0]	O	According to MBIAS register bits. Active State: N/A Synchronous To: spi_clk
TX/RX Channel Setting Signals
txv1_set[15:0]	O	txv1_set[9:0] = TXV1_SET[9:0] txv1_set[15:10] = TXV1_SET[15:10] +/- TXV1_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txv1_bias[2:0]	O	TXV1 channel bias setting. TXV1_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txv1_spare[4:0]	O	Reserved. TXV1_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txv1_off[3:0]	O	TXV1 channel align offset. TXV1_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txv2_set[15:0]	O	txv2_set[9:0] = TXV2_SET[9:0] txv2_set[15:10] = TXV2_SET[15:10] +/- TXV2_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txv2_bias[2:0]	O	TXV2 channel bias setting. TXV2_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txv2_spare[4:0]	O	Reserved. TXV2_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txv2_off[3:0]	O	TXV2 channel align offset. TXV2_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txv3_set[15:0]	O	txv3_set[9:0] = TXV3_SET[9:0] txv3_set[15:10] = TXV3_SET[15:10] +/- TXV3_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txv3_bias[2:0]	O	TXV3 channel bias setting. TXV3_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txv3_spare[4:0]	O	Reserved. TXV3_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txv3_off[3:0]	O	TXV3 channel align offset. TXV3_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txv4_set[15:0]	O	txv4_set[9:0] = TXV4_SET[9:0] txv4_set[15:10] = TXV4_SET[15:10] +/- TXV4_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txv4_bias[2:0]	O	TXV4 channel bias setting. TXV4_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txv4_spare[4:0]	O	Reserved. TXV4_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txv4_off[3:0]	O	TXV4 channel align offset. TXV4_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txh1_set[15:0]	O	txh1_set[9:0] = TXH1_SET[9:0] txh1_set[15:10] = TXH1_SET[15:10] +/- TXH1_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txh1_bias[2:0]	O	TXH1 channel bias setting. TXH1_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txh1_spare[4:0]	O	Reserved. TXH1_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txh1_off[3:0]	O	TXH1 channel align offset. TXH1_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txh2_set[15:0]	O	txh2_set[9:0] = TXH2_SET[9:0] txh2_set[15:10] = TXH2_SET[15:10] +/- TXH2_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txh2_bias[2:0]	O	TXH2 channel bias setting. TXH2_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txh2_spare[4:0]	O	Reserved. TXH2_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txh2_off[3:0]	O	TXH2 channel align offset. TXH2_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txh3_set[15:0]	O	txh3_set[9:0] = TXH3_SET[9:0] txh3_set[15:10] = TXH3_SET[15:10] +/- TXH3_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txh3_bias[2:0]	O	TXH3 channel bias setting. TXH3_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txh3_spare[4:0]	O	Reserved. TXH3_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txh3_off[3:0]	O	TXH3 channel align offset. TXH3_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
txh4_set[15:0]	O	txh4_set[9:0] = TXH4_SET[9:0] txh4_set[15:10] = TXH4_SET[15:10] +/- TXH4_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
txh4_bias[2:0]	O	TXH4 channel bias setting. TXH4_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
txh4_spare[4:0]	O	Reserved. TXH4_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
txh4_off[3:0]	O	TXH4 channel align offset. TXH4_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxv1_set[15:0]	O	rxv1_set[9:0] = RXV1_SET[9:0] rxv1_set[15:10] = RXV1_SET[15:10] +/- RXV1_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxv1_bias[2:0]	O	RXV1 channel bias setting. RXV1_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxv1_spare[4:0]	O	Reserved. RXV1_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxv1_off[3:0]	O	RXV1 channel align offset. RXV1_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxv2_set[15:0]	O	rxv2_set[9:0] = RXV2_SET[9:0] rxv2_set[15:10] = RXV2_SET[15:10] +/- RXV2_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxv2_bias[2:0]	O	RXV2 channel bias setting. RXV2_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxv2_spare[4:0]	O	Reserved. RXV2_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxv2_off[3:0]	O	RXV2 channel align offset. RXV2_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxv3_set[15:0]	O	rxv3_set[9:0] = RXV3_SET[9:0] rxv3_set[15:10] = RXV3_SET[15:10] +/- RXV3_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxv3_bias[2:0]	O	RXV3 channel bias setting. RXV3_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxv3_spare[4:0]	O	Reserved. RXV3_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxv3_off[3:0]	O	RXV3 channel align offset. RXV3_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxv4_set[15:0]	O	rxv4_set[9:0] = RXV4_SET[9:0] rxv4_set[15:10] = RXV4_SET[15:10] +/- RXV4_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxv4_bias[2:0]	O	RXV4 channel bias setting. RXV4_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxv4_spare[4:0]	O	Reserved. RXV4_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxv4_off[3:0]	O	RXV4 channel align offset. RXV4_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxh1_set[15:0]	O	rxh1_set[9:0] = RXH1_SET[9:0] rxh1_set[15:10] = RXH1_SET[15:10] +/- RXH1_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxh1_bias[2:0]	O	RXH1 channel bias setting. RXH1_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxh1_spare[4:0]	O	Reserved. RXH1_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxh1_off[3:0]	O	RXH1 channel align offset. RXH1_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxh2_set[15:0]	O	rxh2_set[9:0] = RXH2_SET[9:0] rxh2_set[15:10] = RXH2_SET[15:10] +/- RXH2_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxh2_bias[2:0]	O	RXH2 channel bias setting. RXH2_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxh2_spare[4:0]	O	Reserved. RXH2_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxh2_off[3:0]	O	RXH2 channel align offset. RXH2_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxh3_set[15:0]	O	rxh3_set[9:0] = RXH3_SET[9:0] rxh3_set[15:10] = RXH3_SET[15:10] +/- RXH3_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxh3_bias[2:0]	O	RXH3 channel bias setting. RXH3_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxh3_spare[4:0]	O	Reserved. RXH3_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxh3_off[3:0]	O	RXH3 channel align offset. RXH3_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
rxh4_set[15:0]	O	rxh4_set[9:0] = RXH4_SET[9:0] rxh4_set[15:10] = RXH4_SET[15:10] +/- RXH4_OFFSET[7:4] Active State: N/A Synchronous To: spi_clk
rxh4_bias[2:0]	O	RXH4 channel bias setting. RXH4_OFFSET[10:8]. Active State: N/A Synchronous To: spi_clk
rxh4_spare[4:0]	O	Reserved. RXH4_OFFSET[15:11]. Active State: N/A Synchronous To: spi_clk
rxh4_off[3:0]	O	RXH4 channel align offset. RXH4_OFFSET[3:0]. Active State: N/A Synchronous To: spi_clk
Oscillator Signals
osc_clk	I	Oscillator input clock. Active State: N/A Synchronous To: None
osc_en	O	Oscillator enable. Active State: High Synchronous To: spi_clk
osc_freq[1:0]	O	Oscillator frequency selection (according to CHIP_INFO[10:9]): 0=80MHz, 1=40MHz, 2=20MHz, 3=OFF. Active State: N/A Synchronous To: spi_clk
ADC Interface
adc_clk	O	ADC clock. Active State: N/A Synchronous To: None
adc_en	O	ADC enable. Active State: High Synchronous To: adc_clk
adc_sp	O	2-clock width to sample analog input. Active State: High Synchronous To: adc_clk
adc_sel[4:0]	O	ADC MUX selection (according to ADC_CFG[15:11]): 5'h1F: VSENS4 5'h1E: VSENS3 5'h1D: VSENS2 5'h1C: VSENS1 5'h1B: UNUSED 5'h1A: VNEG 5'h19: VDDPA 5'h18: DVDD 5'h17: VDD 5'h16: IDC 5'h15: TSENS2 5'h14: TSENS1 5'h13: PREF10 5'h12: PDET10 5'h11: PREF9 5'h10: PDET9 5'h0F: PREF8 5'h0E: PDET8 5'h0D: PREF7 5'h0C: PDET7 5'h0B: PREF6 5'h0A: PDET6 5'h09: PREF5 5'h08: PDET5 5'h07: PREF4 5'h06: PDET4 5'h05: PREF3 5'h04: PDET3 5'h03: PREF2 5'h02: PDET2 5'h01: PREF1 5'h00: PDET1 Active State: N/A Synchronous To: spi_clk
adc_1_bit	I	ADC 1-bit data. Comparator output of Vin > Vdac. Active State: N/A Synchronous To: adc_clk
adc_dac_in[9:0]	O	Successive approximation register output and 10-bit DAC input value respectively. Active State: N/A Synchronous To: adc_clk
adc_aout_sel[1:0]	O	AOUT ADC MUX selection (according to ADC_CFG[5:4]): 0: ADC_MUX 1: cbn1_test 2: vref (v1p5) 3: vcm (v0p9) Active State: N/A Synchronous To: spi_clk
adc_aout_en	O	AOUT multiplexer enable (according to ADC_CFG[3]). Active State: High Synchronous To: spi_clk
adc_lsb_sel	O	Turn down LSB: 0 = LSB is Vref/1023, 1 = LSB is Vref/1055 (according to ADC_CFG[2]). Active State: High Synchronous To: spi_clk
adc_chopper_en	O	Chopper enable (according to ADC_CFG[1]). Active State: High Synchronous To: spi_clk
adc_i_2x	O	Double ADC bias current (according to ADC_CFG[0]). Active State: High Synchronous To: spi_clk
Sensor Interface
sensor_en[15:0]	O	Enable pins for miscellaneous sensors on the chip (according to SENSOR_EN). Active State: N/A Synchronous To: spi_clk
sensor_cfg[15:0]	O	Settings for the on-chip sensors (according to SENSOR_CFG). Active State: N/A Synchronous To: spi_clk
sensor_bias_en	O	sensor_bias_en=1, if any of SENSOR_EN[9:0] are 1. Active State: High Synchronous To: spi_clk
d_tsens_pol	O	Temperature sensor polarization control. Active State: N/A Synchronous To: adc_clk
PCM Interface
pcm_mon_en	O	Reserved. Tied low. Active State: High Synchronous To: None
pcm_ch_sel[1:0]	O	Reserved. Tied low. Active State: High Synchronous To: None
pcm_reset	O	Reserved. Tied low. Active State: High Synchronous To: None
pcm_cntr_en	O	Reserved. Tied low. Active State: High Synchronous To: None
pcm_data_in[11:0]	I	Not connected to logic. Active State: N/A Synchronous To: Asynchronous
OTP Interface
otp_dout[7:0]	O	Bit number to burn during program mode (according to OTP_CFG[12:10], 2^OTP_WR_BIT). Active State: N/A Synchronous To: spi_clk
otp_bank_sel[3:0]	O	OTP read/write address bank select (according to OTP_CFG[9:6]). Active State: N/A Synchronous To: spi_clk
otp_prog	O	OTP program mode enable (according to OTP_CFG[5]). Active State: High Synchronous To: spi_clk
otp_por	O	OTP power-on reset (according to OTP_CFG[4]). Active State: High Synchronous To: spi_clk
otp_cur[1:0]	O	OTP current control (according to OTP_CFG[3:2]). Active State: N/A Synchronous To: spi_clk
otp_read	O	OTP read enable (according to OTP_CFG[1]). Active State: High Synchronous To: spi_clk
otp_en	O	OTP enable (according to OTP_CFG[0]). Active State: High Synchronous To: spi_clk
otp_din[7:0]	I	OTP read data. Data out of the fuse module (of the bank selected by otp_bank_sel). Active State: N/A Synchronous To: spi_clk
Spare Signals
spare[15:0]	O	Reserved (according to TX_RX_SPARE). Active State: High Synchronous To: None