Renesas f641x_dig Register Map/Descriptions

· Name: Control Register

· Description: This register controls and configures chip operation, and is used to start some test modes.

· Size: 16 bits

· Offset: 0x0

· Reset: 0x0049

15:13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSV_15_13	LUT_IND_START	SHIFTREG_ADDR_EN	SHIFTREG_ADDR_PROG	IO_PROTOCOL	ERR_STATUS_BIT	ERR_DET_EN	TAL_RAL_EN	RESET	IO_TEST	MANUAL_EN	SCAN_MODE	SYNC_TRX	TRX_CONT_MODE

Table: CTRL_CFG Register field descriptions

Bits	Name	Access	Description
15:13	RSV_15_13	R/W	For future use Value after reset: 0x0
12	LUT_IND_START	W	1: Sets the LUT pointer for both operationg modes (TX and RX) to the start address defined in HLUT_START (for horizontal polarization) and VLUT_START (for vertical polarization). Value after reset: 0x0
11	SHIFTREG_ADDR_EN	R	1: Shiftreg addr is programmed and effective. Value after reset: 0x0
10	SHIFTREG_ADDR_PROG	W	8-bit shift register is placed between pin_addr[0] (in) and pin_addr[1] (out). To program address, set this bit, then without releasing CSDB send in 8-bit data to pn_addr[0] LSB first. Existing data is pushed out of pin_addr[1]. New chip address = shift_reg[6:0]. Value after reset: 0x0
9	IO_PROTOCOL	R	Set by external pin SPIB/LVDS. It is Read-only bit 1: LVDS (ADD2 defined as SDIB and ADD3 defined as SCLKB, only 2-bits addressing is available) 0: SPI (ADD0-ADD3 are used as Chip addressing) Value after reset: 0x0
8	ERR_STATUS_BIT	R/W1C	1: Error observed 0: No Error observed If you write 1 to the bit, it gets cleared. Writing 0 has no meaning. Value after reset: 0x0
7	ERR_DET_EN	R/W	1: Enable Error Check (additional 16-bits CRC data to be sent at the end) 0: Disable Error Check Value after reset: 0x0
6	TAL_RAL_EN	R/W	Enables the TAL or RAL functionality in a LCL_REG_WR or GBL_REG_WR command: 1: Enabled. 0: Disabled. Value after reset: 0x1
5	RESET	W	1: Resets the chip - auto self-resets to 0 Value after reset: 0x0
4	IO_TEST	W	IO test mode enable for IOs' VIH/VIL test and MOSI's VOL/VOH test, only reset by power-on and hardware reset. In IO test mode, SDO pin is output pin and its logic is CSB OR SCLK OR SDI OR ADD0..3 OR TR OR TLOAD OR RLOAD OR STDBY. Value after reset: 0x0
3	MANUAL_EN	R/W	When set to 1, enable pin of individual channels can be set by CH_ENS bits. When set to 0, all channels are controlled by TRX operation. Value after reset: 0x1
2	SCAN_MODE	W	Scan test mode enable, only reset by power-on and hardware reset. Value after reset: 0x0
1	SYNC_TRX	R/W	1: FEMs and internal SW are controlled by TRX bit (SW_TRX[7]) or TR(pin). Check TRX_CONT_MODE. 0: FEMs and internal SW controlled by SW_TRX. Value after reset: 0x0
0	TRX_CONT_MODE	R/W	1: SPI control. 0: Enable the External Pin Configuration Mode (PIN_CFG Register active). Value after reset: 0x1

CHIP_INFO Register

· Name: Overall Chip Configuration Register

· Description: This register sets the sub-array index of the chip, configures the oscillator, and starts the data transfer from OTP to registers.

· Size: 16 bits

· Offset: 0x1

· Reset: 0x0000

15:8	7:6	5	4	3:0
RSV_15_8	OSC_FREQ	OSC_EN	OTP_FSM_START	SA_INDEX

Table: CHIP_INFO Register field descriptions

Bits	Name	Access	Description
15:8	RSV_15_8	R/W	For future use Value after reset: 0x0
7:6	OSC_FREQ	R/W	Oscillator frequency selection: 0: 80MHz; 1: 40MHz; 2: 20MHz; 3: OFF Value after reset: 0x0
5	OSC_EN	R/W	Oscillator enable. Value after reset: 0x0
4	OTP_FSM_START	W	Start OTP state machine. Value after reset: 0x0
3:0	SA_INDEX	R/W	Sub-array index for the chip. Value after reset: 0x0

PIN_CFG Register

· Name: External Pin Functionality Control Register

· Description:

· Size: 16 bits

· Offset: 0x2

· Reset: 0x0000

15:7	6:2	1:0
RSV_15_7	EXT_PIN_MODE	RSV_1_0

Table: PIN_CFG Register field descriptions

Bits	Name	Access	Description
15:7	RSV_15_7	R/W	For future use Value after reset: 0x0
6:2	EXT_PIN_MODE	R/W	See External Pin CFG tab for explanations - This mode forces all other register/pointers according to the updates of External Pin CFG Value after reset: 0x0
1:0	RSV_1_0	R/W	For future use Value after reset: 0x0

HLUT_INFO Register

· Name: H-LUT Active Index Storage Register

· Description:

· Size: 16 bits

· Offset: 0x3

· Reset: 0x0000

15	14:8	7	6:0
RSV_15	TXH_LUT_IND	RSV_7	RXH_LUT_IND

Table: HLUT_INFO Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R	For future use Value after reset: 0x0
14:8	TXH_LUT_IND	R	Stores the active LUT index for horizontal TX SRAM. This will be updated automatically by the FBS modes and external TLOAD & RLOAD pins. Value after reset: 0x0
7	RSV_7	R	For future use Value after reset: 0x0
6:0	RXH_LUT_IND	R	Stores the active LUT index for horizontal RX SRAM. This will be updated automatically by the FBS modes and external TLOAD and RLOAD pins. Value after reset: 0x0

VLUT_INFO Register

· Name: V-LUT Active Index Storage Register

· Description:

· Size: 16 bits

· Offset: 0x4

· Reset: 0x0000

15	14:8	7	6:0
RSV_15	TXV_LUT_IND	RSV_7	RXV_LUT_IND

Table: VLUT_INFO Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R	For future use Value after reset: 0x0
14:8	TXV_LUT_IND	R	Stores the active LUT index for vertical TX SRAM. This will be updated automatically by the FBS modes and external TLOAD & RLOAD pins. Value after reset: 0x0
7	RSV_7	R	For future use Value after reset: 0x0
6:0	RXV_LUT_IND	R	Stores the active LUT index for vertical RX SRAM. This will be updated automatically by the FBS modes and external TLOAD & RLOAD pins. Value after reset: 0x0

HLUT_START Register

· Name: H-LUT Start Pointer Storage Register

· Description:

· Size: 16 bits

· Offset: 0x5

· Reset: 0x0000

15	14:8	7	6:0
RSV_15	TXH_LUT_START	RSV_7	RXH_LUT_START

Table: HLUT_START Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14:8	TXH_LUT_START	R/W	H-LUT start index for horizontal TX SRAM. The user can change the LUT location starting from this address by TLOAD & RLOAD pins. Value after reset: 0x0
7	RSV_7	R/W	For future use Value after reset: 0x0
6:0	RXH_LUT_START	R/W	H-LUT start index for horizontal RX SRAM. The user can change the LUT location starting from this address by TLOAD & RLOAD pins. Value after reset: 0x0

HLUT_STOP Register

· Name: H-LUT Stop Pointer Storage Register

· Description:

· Size: 16 bits

· Offset: 0x6

· Reset: 0x7F7F

15	14:8	7	6:0
RSV_15	TXH_LUT_STOP	RSV_7	RXH_LUT_STOP

Table: HLUT_STOP Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14:8	TXH_LUT_STOP	R/W	H-LUT stop index for horizontal TX SRAM. The user can change the LUT location up to this address by TLOAD & RLOAD pins. When it reaches to STOP, the pointer goes back to START and continues to be incremented. Value after reset: 0x7F
7	RSV_7	R/W	For future use Value after reset: 0x0
6:0	RXH_LUT_STOP	R/W	H-LUT stop index for horizontal RX SRAM. The user can change the LUT location up to this address by TLOAD & RLOAD pins. When it reaches to STOP, the pointer goes back to START and continues to be incremented. Value after reset: 0x7F

VLUT_START Register

· Name: V-LUT Start Pointer Storage Register

· Description:

· Size: 16 bits

· Offset: 0x7

· Reset: 0x0000

15	14:8	7	6:0
RSV_15	TXV_LUT_START	RSV_7	RXV_LUT_START

Table: VLUT_START Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14:8	TXV_LUT_START	R/W	V-LUT start index for vertical TX SRAM. The user can change the LUT location starting from this address by TLOAD & RLOAD pins. Value after reset: 0x0
7	RSV_7	R/W	For future use Value after reset: 0x0
6:0	RXV_LUT_START	R/W	V-LUT start index for vertical RX SRAM. The user can change the LUT location starting from this address by TLOAD & RLOAD pins. Value after reset: 0x0

VLUT_STOP Register

· Name: V-LUT Stop Pointer Storage Register

· Description:

· Size: 16 bits

· Offset: 0x8

· Reset: 0x7F7F

15	14:8	7	6:0
RSV_15	TXV_LUT_STOP	RSV_7	RXV_LUT_STOP

Table: VLUT_STOP Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14:8	TXV_LUT_STOP	R/W	V-LUT stop index for vertical TX SRAM. The user can change the LUT location up to this address by TLOAD & RLOAD pins. When it reaches to STOP, the pointer goes back to START and continues to be incremented. Value after reset: 0x7F
7	RSV_7	R/W	For future use Value after reset: 0x0
6:0	RXV_LUT_STOP	R/W	V-LUT stop index for vertical RX SRAM. The user can change the LUT location up to this address by TLOAD & RLOAD pins. When it reaches to STOP, the pointer goes back to START and continues to be incremented. Value after reset: 0x7F

BIST Register

· Name: SRAM BIST Register

· Description: Triggers
- the memory self-test of the selected look-up table (LUT), and provides status information accordingly.
- a cyclic redundancy check (CRC) of the content of the selected LUT, whereas the resulting check bits are written to the CRC_RESULT register.
- an initialization of the selected LUT with all bits set to 0.

· Size: 16 bits

· Offset: 0x9

· Reset: 0x0000

15:12	11	10:8	7:5	4:3	2	1	0
RSV_15_12	SRAM_DONE	SRAM_ERR	RSV_7_5	SRAM_SEL	SRAM_CRC	SRAM_BIST	SRAM_INIT

Table: BIST Register field descriptions

Bits	Name	Access	Description
15:12	RSV_15_12	R	For future use Value after reset: 0x0
11	SRAM_DONE	R	SRAM access (initialization, BIST or CRC) status: 0: When any of SRAM_CRC or SRAM_BIST or SRAM INIT is set to 1, an SRAM access is ongoing. Otherwise, there is no SRAM access ongoing. 1: SRAM access is done. Value after reset: 0x0
10:8	SRAM_ERR	R	Number of SRAM errors during LUT BIST: 0: No error. 4: One stuck-at '1' fault at an even or one stuck-at '0' fault at an odd bit location. 5: One stuck-at '1' fault at an odd or one stuck-at '0' fault at an even bit location. 7: More than one error occurred. Value after reset: 0x0
7:5	RSV_7_5	R	For future use Value after reset: 0x0
4:3	SRAM_SEL	R/W	00: Vertical TX SRAM. 01: Horizontal TX SRAM. 10: Vertical RX SRAM. 11: Horizontal RX SRAM. Value after reset: 0x0
2	SRAM_CRC	R/W	SRAM CRC check request by writing 1. The SRAM CRC algorithm is as follows: 1. Initial value => 16'hFFFF 2. CRC generator polynomial => x16 + x12 + x5 +1 3. The bits sequence are a. N=SRAM_SEL[4:3], ADDR=0. b. Get data from LUT[N](ADDR). c. Calculate CRC for each channel starting with MSB. d. If ADDR=2^7-1, finish CRC check. Otherwise, ADDR=ADDR+1 and go to step b. Value after reset: 0x0
1	SRAM_BIST	R/W	SRAM BIST request. Request SRAM BIST by writing 1. Value after reset: 0x0
0	SRAM_INIT	R/W	SRAM initialization request. Request SRAM initialization (all of SRAM data is initialized to "0") by writing 1. Value after reset: 0x0

CRC_RESULT Register

· Name: SRAM CRC Result Register

· Description: Stores the resulting check bits of the latest cyclic redundancy check (CRC) of the content of the LUT (SRAM) that is selected in BIST[4:3] (SRAM_SEL[1:0]).

· Size: 16 bits

· Offset: 0xA

· Reset: 0xFFFF

15:0

CRC_RESULT

Table: CRC_RESULT Register field descriptions

Bits	Name	Access	Description
15:0	CRC_RESULT	R	16-bit SRAM CRC result. Value after reset: 0xFFFF

SW_TRX Register

· Name: TRX Switch Control Register

· Description: Controls and configures TRX switch operation.

· Size: 16 bits

· Offset: 0xB

· Reset: 0x0C00

15:12	11	10	9	8	7	6	5	4	3	2	1	0
RSV_15_12	MB_EN	STANDBY	H_POL_EN	V_POL_EN	TRX	SW_FEM_TR_MODE	SW_DRV_TR_STATE	SW_DRV_EN_TR	TRX_EXTH	TRX_EXTV	TRX_BFH	TRX_BFV

Table: SW_TRX Register field descriptions

Bits	Name	Access	Description
15:12	RSV_15_12	R/W	For future use Value after reset: 0x0
11	MB_EN	R/W	Chip reference bias enable. 0: Chip bias disable. 1: Chip bias enable. Value after reset: 0x1
10	STANDBY	R/W	Put the chip in Standby Mode (all ENs off). Value after reset: 0x1
9	H_POL_EN	R/W	When set to 1, channels with horizontal polarization are enabled. Value after reset: 0x0
8	V_POL_EN	R/W	When set to 1, channels with vertical polarization are enabled. Value after reset: 0x0
7	TRX	R/W	Soft TRX Control. 1: TX 0: RX This bit is overwritten by TR Pin if CTRL_CFG[0]=0. (State of the TR pin can be read back from this bit.) Value after reset: 0x0
6	SW_FEM_TR_MODE	R/W	0: Negative pins are floating, 1: Positive pins are floating Value after reset: 0x0
5	SW_DRV_TR_STATE	R/W	0: Outputs are "GND", 1: Outputs are High/Low Value after reset: 0x0
4	SW_DRV_EN_TR	R/W	0: TRX pins for FEMs are disabled (float), 1: In use Value after reset: 0x0
3	TRX_EXTH	R/W	1: TX, 0: RX. This bit controls the external FEM SWs for horizontal polarization. Value after reset: 0x0
2	TRX_EXTV	R/W	1: TX, 0: RX. This bit controls the external FEM SWs for vertical polarization. Value after reset: 0x0
1	TRX_BFH	R/W	1: TX, 0: RX. This bit controls the BF SWs for horizontal polarization. Value after reset: 0x0
0	TRX_BFV	R/W	1: TX, 0: RX. This bit controls the BF SWs for vertical polarization. Value after reset: 0x0

CH_ENS Register

· Name: Power-enable TRX Register

· Description:

· Size: 16 bits

· Offset: 0xC

· Reset: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXH4_EN	RXH3_EN	RXH2_EN	RXH1_EN	RXV4_EN	RXV3_EN	RXV2_EN	RXV1_EN	TXH4_EN	TXH3_EN	TXH2_EN	TXH1_EN	TXV4_EN	TXV3_EN	TXV2_EN	TXV1_EN

Table: CH_ENS Register field descriptions

Bits	Name	Access	Description
15	RXH4_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
14	RXH3_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
13	RXH2_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
12	RXH1_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
11	RXV4_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
10	RXV3_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
9	RXV2_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
8	RXV1_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
7	TXH4_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
6	TXH3_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
5	TXH2_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
4	TXH1_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
3	TXV4_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
2	TXV3_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
1	TXV2_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0
0	TXV1_EN	R/W	1: Enable, 0: Disable Value after reset: 0x0

CHIP_ID Register

· Name: Chip ID Register

· Description: This is an informational read-only register.

· Size: 16 bits

· Offset: 0xD

· Reset: 0x0000

15:14	13:12	11:8	7:4	3:0
ID_CLASS	ID_FREQ	BASE_REV	METAL_REV	VARIANTS

Table: CHIP_ID Register field descriptions

Bits	Name	Access	Description
15:14	ID_CLASS	R	0: Beamformer Value after reset: 0x0
13:12	ID_FREQ	R	0: X/KU 1: KU 2: KA Value after reset: 0x0
11:8	BASE_REV	R	Code for base variants. Value after reset: 0x0
7:4	METAL_REV	R	Code for metal variants. Value after reset: 0x0
3:0	VARIANTS	R	Code for variants. Value after reset: 0x0

MBIAS Register

· Name: Master Bias Control Register

· Description: All the bits from this register are going to be outputs (digital to analog) and they are used to adjust master bias settings. It should be noted that MBIAS[0] = 1 is required for whole chip to be powered up.

· Size: 16 bits

· Offset: 0xE

· Reset: 0x0093

15:8	7:5	4:2	1	0
RSV_15_8	PTAT2_SLOPE	PTADJ	MB_BG_SEL	MB_EN

Table: MBIAS Register field descriptions

Bits	Name	Access	Description
15:8	RSV_15_8	R/W	For future use Value after reset: 0x0
7:5	PTAT2_SLOPE	R/W	PTAT2 slope control. Value after reset: 0x4
4:2	PTADJ	R/W	Internal reference current generator level control. +/- 30% reference current control adjustment. Value after reset: 0x4
1	MB_BG_SEL	R/W	0: BG source from PTAT generator. 1: BG source from POR. Value after reset: 0x1
0	MB_EN	R	Chip reference bias enable. 0: Chip bias disable. 1: Chip bias enable. Shadow bit of SW_TRX[11] (MB_EN). Value after reset: 0x1

CLK_CFG Register

· Name: ADC Clock Control Register

· Description: The ADC Clock Control register configures the ADC clock and determines the delay between ADC operation trigger and the start of the aquisition phase.

· Size: 16 bits

· Offset: 0xF

· Reset: 0xFB30

15:12	11:8	7:4	3:0
ADC_START_DELAY	BASE_CLK_CTRL	ADC_CLK_HIGH	ADC_CLK_LOW

Table: CLK_CFG Register field descriptions

Bits	Name	Access	Description
15:12	ADC_START_DELAY	R/W	Determines the delay between ADC source selection and aquisition start in multiples of ADC clock (adc_clk) cycles. Value after reset: 0xF
11:8	BASE_CLK_CTRL	R/W	Select base clock (BASE_CLK) as OSC_FREQ/(N+1). Value after reset: 0xB
7:4	ADC_CLK_HIGH	R/W	Select ADC clock's high width as BASE_CLK*(N+1). Value after reset: 0x3
3:0	ADC_CLK_LOW	R/W	Select ADC clock's low width as BASE_CLK*(N+1). Value after reset: 0x0

ADC_CFG Register

· Name: ADC Control Register

· Description: The ADC Control register configures the ADC and selects the operation mode.

· Size: 16 bits

· Offset: 0x10

· Reset: 0x0380

15:11	10	9:7	6	5:4	3	2	1	0
ADC_SEL	ADC_SEL_SOURCE	ADC_AVG	PD_DIFF_MODE	ADC_AOUT_SEL	ADC_AOUT_EN	LSB_SEL	CHOPPER_EN	ADC_I_2X

Table: ADC_CFG Register field descriptions

Bits	Name	Access	Description
15:11	ADC_SEL	R/W	ADC Mux Selection Bits: 5'h1F: VSENS4 5'h1E: VSENS3 5'h1D: VSENS2 5'h1C: VSENS1 5'h1B: UNUSED 5'h1A: VNEG 5'h19: VDDPA 5'h18: DVDD 5'h17: VDD 5'h16: IDC 5'h15: TSENS2 5'h14: TSENS1 5'h13: PREF10 5'h12: PDET10 5'h11: PREF9 5'h10: PDET9 5'h0F: PREF8 5'h0E: PDET8 5'h0D: PREF7 5'h0C: PDET7 5'h0B: PREF6 5'h0A: PDET6 5'h09: PREF5 5'h08: PDET5 5'h07: PREF4 5'h06: PDET4 5'h05: PREF3 5'h04: PDET3 5'h03: PREF2 5'h02: PDET2 5'h01: PREF1 5'h00: PDET1 Value after reset: 0x0
10	ADC_SEL_SOURCE	R/W	ADC mux selector source 0: FSM - SRQ 1: ADC_SEL Value after reset: 0x0
9:7	ADC_AVG	R/W	0: No averaging 1-6: Averaging count = 2^ADC_AVG 7: Averaging count = 2^6 Value after reset: 0x7
6	PD_DIFF_MODE	R/W	1: No difference. PDET data are stored as measured. PDET(reg) = PDET(meas). 0: Difference between PREF and PDET is stored. PDET(reg) = PREF(meas) - PDET(meas). Value after reset: 0x0
5:4	ADC_AOUT_SEL	R/W	AOUT ADC Mux Selection Bits: 0: ADC_MUX 1: cbn1_test 2: vref(v1p5) 3: vcm(v0p9) Value after reset: 0x0
3	ADC_AOUT_EN	R/W	Enable AOUT mux Value after reset: 0x0
2	LSB_SEL	R/W	Turn down LSB 0=LSB is Vref/1023, 1=LSB is Vref/1055 Value after reset: 0x0
1	CHOPPER_EN	R/W	Chopper Enable Value after reset: 0x0
0	ADC_I_2X	R/W	Double ADC bias current Value after reset: 0x0

ADC_SRQ1 Register

· Name: Sensor Activation Register - 1

· Description: This register controls the on-chip sensor activities. Writing 1 to any bit of this register triggers the whole sequence for the corresponding sensor measurement. It enables the oscillator, sets the ADC channel, performs conversion, and writes the result to corresponding ADC Data register.
ADC settings for any of these activities are controlled by CLK_CFG and ADC_CFG registers.

· Size: 16 bits

· Offset: 0x11

· Reset: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSENS_3_4	VSENS_1_2	VSENS_NEG	DC_SENS	TSENS2	TSENS1	PDET_RFC_H	PDET_TX4_H	PDET_TX3_H	PDET_TX2_H	PDET_TX1_H	PDET_RFC_V	PDET_TX4_V	PDET_TX3_V	PDET_TX2_V	PDET_TX1_V

Table: ADC_SRQ1 Register field descriptions

Bits	Name	Access	Description
15	VSENS_3_4	W	Reads VSENS3 and VSENS4 external pins (ADC_SEL 0x1E, 0x1F) Value after reset: 0x0
14	VSENS_1_2	W	Reads VSENS1 and VSENS2 external pins (ADC_SEL 0x1C, 0x1D) Value after reset: 0x0
13	VSENS_NEG	W	Reads the -5V voltage supply (ADC_SEL 0x1A) Value after reset: 0x0
12	DC_SENS	W	Reads VDD, DVDD, VDDPA and current sensors (ADC_SEL 0x16, 0x17, 0x18, 0x19) Value after reset: 0x0
11	TSENS2	W	Reads TSENS2 (ADC_SEL 0x15) Value after reset: 0x0
10	TSENS1	W	Reads TSENS1 (ADC_SEL 0x14) Value after reset: 0x0
9	PDET_RFC_H	W	Reads PDET10 and PREF10 (ADC_SEL 0x12, 0x13) Value after reset: 0x0
8	PDET_TX4_H	W	Reads PDET9 and PREF9 (ADC_SEL 0x10, 0x11) Value after reset: 0x0
7	PDET_TX3_H	W	Reads PDET8 and PREF8 (ADC_SEL 0x0E, 0x0F) Value after reset: 0x0
6	PDET_TX2_H	W	Reads PDET7 and PREF7 (ADC_SEL 0x0C, 0x0D) Value after reset: 0x0
5	PDET_TX1_H	W	Reads PDET6 and PREF6 (ADC_SEL 0x0A, 0x0B) Value after reset: 0x0
4	PDET_RFC_V	W	Reads PDET5 and PREF5 (ADC_SEL 0x08, 0x09) Value after reset: 0x0
3	PDET_TX4_V	W	Reads PDET4 and PREF4 (ADC_SEL 0x06, 0x07) Value after reset: 0x0
2	PDET_TX3_V	W	Reads PDET3 and PREF3 (ADC_SEL 0x04, 0x05) Value after reset: 0x0
1	PDET_TX2_V	W	Reads PDET2 and PREF2 (ADC_SEL 0x02, 0x03) Value after reset: 0x0
0	PDET_TX1_V	W	Reads PDET1 and PREF1 (ADC_SEL 0x00, 0x01) Value after reset: 0x0

ADC_SRQ2 Register

· Name: Sensor Activation Register - 2

· Description:

· Size: 16 bits

· Offset: 0x12

· Reset: 0x0000

15:13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSV_15_13	RSV_12	RSV_11	RSV_10	RSV_9	RSV_8	RSV_7	RSV_6	RSV_5	RSV_4	RSV_3	RSV_2	RSV_1	RSV_0

Table: ADC_SRQ2 Register field descriptions

Bits	Name	Access	Description
15:13	RSV_15_13	W	For future use Value after reset: 0x0
12	RSV_12	W	For future use Value after reset: 0x0
11	RSV_11	W	For future use Value after reset: 0x0
10	RSV_10	W	For future use Value after reset: 0x0
9	RSV_9	W	For future use Value after reset: 0x0
8	RSV_8	W	For future use Value after reset: 0x0
7	RSV_7	W	For future use Value after reset: 0x0
6	RSV_6	W	For future use Value after reset: 0x0
5	RSV_5	W	For future use Value after reset: 0x0
4	RSV_4	W	For future use Value after reset: 0x0
3	RSV_3	W	For future use Value after reset: 0x0
2	RSV_2	W	For future use Value after reset: 0x0
1	RSV_1	W	For future use Value after reset: 0x0
0	RSV_0	W	For future use Value after reset: 0x0

SENSOR_EN Register

· Name: Sensor Enable Register

· Description: Enable pins for miscellaneous sensors on the chip.
[0] : PDET_TX1_V_EN (1: ADC_SRQ1[0]=1, 0: at the end of serial poll)
[1] : PDET_TX2_V_EN(1: ADC_SRQ1[1]=1, 0: at the end of serial poll)
...

· Size: 16 bits

· Offset: 0x13

· Reset: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSENS_3_4_EN	VSENS_1_2_EN	VSENS_NEG_EN	DC_SENS_EN	TSENS2_EN	TSENS1_EN	PDET_RFC_H_EN	PDET_TX4_H_EN	PDET_TX3_H_EN	PDET_TX2_H_EN	PDET_TX1_H_EN	PDET_RFC_V_EN	PDET_TX4_V_EN	PDET_TX3_V_EN	PDET_TX2_V_EN	PDET_TX1_V_EN

Table: SENSOR_EN Register field descriptions

Bits	Name	Access	Description
15	VSENS_3_4_EN	R/W	Sensor enable for VSENS3 and VSENS4 Value after reset: 0x0
14	VSENS_1_2_EN	R/W	Sensor enable for VSENS1 and VSENS2 Value after reset: 0x0
13	VSENS_NEG_EN	R/W	Sensor enable for -5V voltage supply Value after reset: 0x0
12	DC_SENS_EN	R/W	Sensor enable for VDD, DVDD, VDDPA and current sensors Value after reset: 0x0
11	TSENS2_EN	R/W	Sensor enable for TSENS2 Value after reset: 0x0
10	TSENS1_EN	R/W	Sensor enable for TSENS1 Value after reset: 0x0
9	PDET_RFC_H_EN	R/W	Sensor enable for PDET10 and PREF10 Value after reset: 0x0
8	PDET_TX4_H_EN	R/W	Sensor enable for PDET9 and PREF9 Value after reset: 0x0
7	PDET_TX3_H_EN	R/W	Sensor enable PDET8 and PREF8 Value after reset: 0x0
6	PDET_TX2_H_EN	R/W	Sensor enable for PDET7 and PREF7 Value after reset: 0x0
5	PDET_TX1_H_EN	R/W	Sensor enable for PDET6 and PREF6 Value after reset: 0x0
4	PDET_RFC_V_EN	R/W	Sensor enable for PDET5 and PREF5 Value after reset: 0x0
3	PDET_TX4_V_EN	R/W	Sensor enable for PDET4 and PREF4 Value after reset: 0x0
2	PDET_TX3_V_EN	R/W	Sensor enable for PDET3 and PREF3 Value after reset: 0x0
1	PDET_TX2_V_EN	R/W	Sensor enable for PDET2 and PREF2 Value after reset: 0x0
0	PDET_TX1_V_EN	R/W	Sensor enable for PDET1 and PREF1 Value after reset: 0x0

SENSOR_CFG Register

· Name: Sensor Configuration Register

· Description: Defines the settings for the on-chip sensors and controls temperature sensor polarization.

· Size: 16 bits

· Offset: 0x14

· Reset: 0x0524

15:14	13:12	11	10:9	8:7	6:4	3:1	0
IREF_SEL	TSENS_POL_CFG	RSV_11	PDET_BUFF_PROF	PDET_CORE_PROF	PDET_CORE_BIAS	PDET_BUFFER_BIAS	PDET_EN

Table: SENSOR_CFG Register field descriptions

Bits	Name	Access	Description
15:14	IREF_SEL	R/W	00: BG 01: PTAT 10: PTAT2 11 - TBD Value after reset: 0x0
13:12	TSENS_POL_CFG	R/W	Temperature sensor polarization control: 00: Averaging as defined in the tab "diagram". 01: Pol 0 only. 10: Pol 1 only. 11: Unused. Value after reset: 0x0
11	RSV_11	R/W	For future use Value after reset: 0x0
10:9	PDET_BUFF_PROF	R/W	Buffer current profile Value after reset: 0x2
8:7	PDET_CORE_PROF	R/W	Core current profile Value after reset: 0x2
6:4	PDET_CORE_BIAS	R/W	Block bias tune Value after reset: 0x2
3:1	PDET_BUFFER_BIAS	R/W	Block bias tune Value after reset: 0x2
0	PDET_EN	R/W	Block Enable Value after reset: 0x0

SCRATCH Register

· Name: Scratch Register

· Description: 2 bytes of memory for arbitrary data storage. This data does not affect the operation of the device.

· Size: 16 bits

· Offset: 0x15

· Reset: 0x0000

15:0

SCRATCH

Table: SCRATCH Register field descriptions

Bits	Name	Access	Description
15:0	SCRATCH	R/W	Reserved for random r/w by the user. Value after reset: 0x0

TXVn_SET (for n = 1; n <= 4) Register

· Name: TXVn Set Register

· Description: Phase/Gain control bits for each TX channel with vertical polarization.
These registers have shadow registers and the values get updated from buffer to active registers only with an TX RF Load trigger through SPI command or external pin (TLOAD).

· Size: 16 bits

· Offset: 0x16 + (n-1)*0x1

· Reset: 0x003F

15:8	7:0
TX_PHASE_CTRL	TX_GAIN_CTRL

Table: TXVn_SET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:8	TX_PHASE_CTRL	R/W	Phase set. TXn_SET[9:8] bits are used for trimming. Value after reset: 0x0
7:0	TX_GAIN_CTRL	R/W	Gain set Value after reset: 0x3F

TXHn_SET (for n = 1; n <= 4) Register

· Name: TXHn Set Register

· Description: Phase/Gain control bits for each TX channel with horizontal polarization.
These registers have shadow registers and the values get updated from buffer to active registers only with an TX RF Load trigger through SPI command or external pin (TLOAD).

· Size: 16 bits

· Offset: 0x1A + (n-1)*0x1

· Reset: 0x003F

15:8	7:0
TX_PHASE_CTRL	TX_GAIN_CTRL

Table: TXHn_SET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:8	TX_PHASE_CTRL	R/W	Phase set. TXn_SET[9:8] bits are used for trimming. Value after reset: 0x0
7:0	TX_GAIN_CTRL	R/W	Gain set Value after reset: 0x3F

RXVn_SET (for n = 1; n <= 4) Register

· Name: RXVn Set Register

· Description: Phase/Gain control bits for each RX channel with vertical polarization.
These registers have shadow registers and the values get updated from buffer to active registers only with an RX RF Load trigger through SPI command or external pin (RLOAD).

· Size: 16 bits

· Offset: 0x1E + (n-1)*0x1

· Reset: 0x003F

15:8	7:0
RX_PHASE_CTRL	RX_GAIN_CTRL

Table: RXVn_SET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:8	RX_PHASE_CTRL	R/W	Phase set. TXn_SET[9:8] bits are used for trimming. Value after reset: 0x0
7:0	RX_GAIN_CTRL	R/W	Gain set Value after reset: 0x3F

RXHn_SET (for n = 1; n <= 4) Register

· Name: RXHn Set Register

· Description: Phase/Gain control bits for each RX channel with horizontal polarization.
These registers have shadow registers and the values get updated from buffer to active registers only with an RX RF Load trigger through SPI command or external pin (RLOAD).

· Size: 16 bits

· Offset: 0x22 + (n-1)*0x1

· Reset: 0x003F

15:8	7:0
RX_PHASE_CTRL	RX_GAIN_CTRL

Table: RXHn_SET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:8	RX_PHASE_CTRL	R/W	Phase set. TXn_SET[9:8] bits are used for trimming. Value after reset: 0x0
7:0	RX_GAIN_CTRL	R/W	Gain set Value after reset: 0x3F

TXVn_OFFSET (for n = 1; n <= 4) Register

· Name: TXVn Offset Register

· Description: TX offset register for vertical polarization.
The phase offset (TX_PH_OFF) is stored in twos (2s) complement format, whereas channel bias (TX_CH_BIAS) and align offset (TX_ALIGN_OFF) are stored as absolute values.

· Size: 16 bits

· Offset: 0x26 + (n-1)*0x1

· Reset: 0x0408

15:14	13:11	10:8	7:4	3:0
RSV_15_14	PDET_ATEST_CTRL	TX_CH_BIAS	TX_PH_OFF	TX_ALIGN_OFF

Table: TXVn_OFFSET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:14	RSV_15_14	R/W	For future use. Spare bits for analog. Value after reset: 0x0
13:11	PDET_ATEST_CTRL	R/W	Controls the testing scheme Value after reset: 0x0
10:8	TX_CH_BIAS	R/W	Channel bias setting. Note: This is not really an offset value as the register name may suggest, but an absolute value. Value after reset: 0x4
7:4	TX_PH_OFF	R/W	Phase offset. The data stored is 2s complement format. Value after reset: 0x0
3:0	TX_ALIGN_OFF	R/W	Align offset. The data stored is absolute value. Value after reset: 0x8

TXHn_OFFSET (for n = 1; n <= 4) Register

· Name: TXHn Offset Register

· Description: TX offset register for horizontal polarization.
The phase offset (TX_PH_OFF) is stored in twos (2s) complement format, whereas channel bias (TX_CH_BIAS) and align offset (TX_ALIGN_OFF) are stored as absolute values.

· Size: 16 bits

· Offset: 0x2A + (n-1)*0x1

· Reset: 0x0408

15:14	13:11	10:8	7:4	3:0
RSV_15_14	PDET_ATEST_CTRL	TX_CH_BIAS	TX_PH_OFF	TX_ALIGN_OFF

Table: TXHn_OFFSET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:14	RSV_15_14	R/W	For future use. Spare bits for analog. Value after reset: 0x0
13:11	PDET_ATEST_CTRL	R/W	Controls the testing scheme Value after reset: 0x0
10:8	TX_CH_BIAS	R/W	Channel bias setting. Note: This is not really an offset value as the register name may suggest, but an absolute value. Value after reset: 0x4
7:4	TX_PH_OFF	R/W	Phase offset. The data stored is 2s complement format. Value after reset: 0x0
3:0	TX_ALIGN_OFF	R/W	Align offset. The data stored is absolute value. Value after reset: 0x8

RXVn_OFFSET (for n = 1; n <= 4) Register

· Name: RXVn Offset Register

· Description: RX offset register for vertical polarization.
The phase offset (RX_PH_OFF) is stored in twos (2s) complement format, whereas channel bias (RX_CH_BIAS) and align offset (RX_ALIGN_OFF) are stored as absolute values.

· Size: 16 bits

· Offset: 0x2E + (n-1)*0x1

· Reset: 0x0408

15:11	10:8	7:4	3:0
RSV_15_11	RX_CH_BIAS	RX_PH_OFF	RX_ALIGN_OFF

Table: RXVn_OFFSET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:11	RSV_15_11	R/W	For future use. Spare bits for analog. Value after reset: 0x0
10:8	RX_CH_BIAS	R/W	Channel bias setting. Note: This is not really an offset value as the register name may suggest, but an absolute value. Value after reset: 0x4
7:4	RX_PH_OFF	R/W	Phase offset. The data stored is 2s complement format. Value after reset: 0x0
3:0	RX_ALIGN_OFF	R/W	Align offset. The data stored is absolute value. Value after reset: 0x8

RXHn_OFFSET (for n = 1; n <= 4) Register

· Name: RXHn Offset Register

· Description: RX offset register for horizontal polarization.
The phase offset (RX_PH_OFF) is stored in twos (2s) complement format, whereas channel bias (RX_CH_BIAS) and align offset (RX_ALIGN_OFF) are stored as absolute values.

· Size: 16 bits

· Offset: 0x32 + (n-1)*0x1

· Reset: 0x0408

15:11	10:8	7:4	3:0
RSV_15_11	RX_CH_BIAS	RX_PH_OFF	RX_ALIGN_OFF

Table: RXHn_OFFSET (for n = 1; n <= 4) Register field descriptions

Bits	Name	Access	Description
15:11	RSV_15_11	R/W	For future use. Spare bits for analog. Value after reset: 0x0
10:8	RX_CH_BIAS	R/W	Channel bias setting. Note: This is not really an offset value as the register name may suggest, but an absolute value. Value after reset: 0x4
7:4	RX_PH_OFF	R/W	Phase offset. The data stored is 2s complement format. Value after reset: 0x0
3:0	RX_ALIGN_OFF	R/W	Align offset. The data stored is absolute value. Value after reset: 0x8

TXCOM_TUNE Register

· Name: TX Common Tune Register

· Description:

· Size: 16 bits

· Offset: 0x36

· Reset: 0x1520

15:14	13	12:11	10:9	8:6	5:4	3:2	1:0
TX_PA_C2B	TX_PA_RFB	TX_PA_RBB1	TX_DA_CISM1	TX_DA_RIM1	TX_DA_CIM1	TX_AMP_TUNE	TX_VGA_TUNE

Table: TXCOM_TUNE Register field descriptions

Bits	Name	Access	Description
15:14	TX_PA_C2B	R/W	Block bias tune Value after reset: 0x0
13	TX_PA_RFB	R/W	Amp frequency tuning bits Value after reset: 0x0
12:11	TX_PA_RBB1	R/W	PA frequency tuning bits Value after reset: 0x2
10:9	TX_DA_CISM1	R/W	Block bias tune Value after reset: 0x2
8:6	TX_DA_RIM1	R/W	Amp frequency tuning bits Value after reset: 0x4
5:4	TX_DA_CIM1	R/W	PA frequency tuning bits Value after reset: 0x2
3:2	TX_AMP_TUNE	R/W	DA frequency tuning bits Value after reset: 0x0
1:0	TX_VGA_TUNE	R/W	VGA frequency tuning bits Value after reset: 0x0

TXCOM_CFG Register

· Name: TX Common Configuration Register

· Description:

· Size: 16 bits

· Offset: 0x37

· Reset: 0x01E0

15	14	13	12:10	9	8	7	6	5	4	3	2	1	0
RSV_15	RSV_14	TX_CASC_EN	PDET_ATEST_CTRL	PDET_DIFF	TX_VGA_PT	TX_AMP_BG	TX_DA_PT	TX_PA_BG	TX_VGA_EN	TX_AMP_EN	TX_DA_EN	TX_PA_EN	PHASE_OFFSET_EN

Table: TXCOM_CFG Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14	RSV_14	R/W	For future use Value after reset: 0x0
13	TX_CASC_EN	R/W	Cascode Enable Value after reset: 0x0
12:10	PDET_ATEST_CTRL	R/W	Controls the testing scheme Value after reset: 0x0
9	PDET_DIFF	R/W	PDET Diff enable Value after reset: 0x0
8	TX_VGA_PT	R/W	Temp Profile Select Value after reset: 0x1
7	TX_AMP_BG	R/W	Temp Profile Select Value after reset: 0x1
6	TX_DA_PT	R/W	Temp Profile Select Value after reset: 0x1
5	TX_PA_BG	R/W	Temp Profile Select Value after reset: 0x1
4	TX_VGA_EN	R/W	Block Enable Value after reset: 0x0
3	TX_AMP_EN	R/W	Block Enable Value after reset: 0x0
2	TX_DA_EN	R/W	Block Enable Value after reset: 0x0
1	TX_PA_EN	R/W	Block Enable Value after reset: 0x0
0	PHASE_OFFSET_EN	R/W	Phase offset Enable Value after reset: 0x0

TXCOM_BIAS1 Register

· Name: TX Common Bias1 Register

· Description:

· Size: 16 bits

· Offset: 0x38

· Reset: 0x4924

15	14:12	11:9	8:6	5:3	2:0
RSV_15	TX_PS_BIAS	TX_VGA_BIAS	TX_AMP_BIAS	TX_DA_BIAS	TX_PA_BIAS

Table: TXCOM_BIAS1 Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14:12	TX_PS_BIAS	R/W	For future use Value after reset: 0x4
11:9	TX_VGA_BIAS	R/W	TX Amp Bias Current Value after reset: 0x4
8:6	TX_AMP_BIAS	R/W	TX PA Bias Current Value after reset: 0x4
5:3	TX_DA_BIAS	R/W	TX DA Bias Current Value after reset: 0x4
2:0	TX_PA_BIAS	R/W	TX VGA Bias Current Value after reset: 0x4

TXCOM_BIAS2 Register

· Name: TX Common Bias2 Register

· Description:

· Size: 16 bits

· Offset: 0x39

· Reset: 0x024A

15:11	10	9:7	6:4	3:2	1:0
RSV_15_11	RSV_10	TX_VGA_CASC_BIAS	TX_AMP_CASC_BIAS	TX_DA_CASC_BIAS	TX_PA_CASC_BIAS

Table: TXCOM_BIAS2 Register field descriptions

Bits	Name	Access	Description
15:11	RSV_15_11	R/W	For future use Value after reset: 0x0
10	RSV_10	R/W	For future use Value after reset: 0x0
9:7	TX_VGA_CASC_BIAS	R/W	For future use Value after reset: 0x4
6:4	TX_AMP_CASC_BIAS	R/W	TX PA Cascode Bias Voltage Value after reset: 0x4
3:2	TX_DA_CASC_BIAS	R/W	TX DA Cascode Bias Voltage Value after reset: 0x2
1:0	TX_PA_CASC_BIAS	R/W	TX Aligner Bias Current Value after reset: 0x2

RXCOM_TUNE Register

· Name: RX Common Tune Register

· Description:

· Size: 16 bits

· Offset: 0x3A

· Reset: 0x0000

15:12	11:8	7:6	5:4	3:2	1:0
RSV_15_12	RSV_11_8	RX_AMP_TUNE	RX_VGA_TUNE	RX_LNA2_TUNE	RX_LNA1_TUNE

Table: RXCOM_TUNE Register field descriptions

Bits	Name	Access	Description
15:12	RSV_15_12	R/W	For future use Value after reset: 0x0
11:8	RSV_11_8	R/W	For future use Value after reset: 0x0
7:6	RX_AMP_TUNE	R/W	Amp frequency tuning bits Value after reset: 0x0
5:4	RX_VGA_TUNE	R/W	Amp frequency tuning bits Value after reset: 0x0
3:2	RX_LNA2_TUNE	R/W	Amp frequency tuning bits Value after reset: 0x0
1:0	RX_LNA1_TUNE	R/W	Amp frequency tuning bits Value after reset: 0x0

RXCOM_CFG Register

· Name: RX Common Configuration Register

· Description:

· Size: 16 bits

· Offset: 0x3B

· Reset: 0x0F00

15:14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSV_15_14	RX_CASC_EN	RSV_12	RX_AMP_PT	RX_VGA_PT	RX_LNA2_PT	RX_LNA1_PT	RX_AMP_EN	RX_VGA_EN	RX_LNA2_EN	RX_LNA1_EN	RSV_3	RSV_2	HIGH_LIN_MODE	PHASE_OFFSET_EN

Table: RXCOM_CFG Register field descriptions

Bits	Name	Access	Description
15:14	RSV_15_14	R/W	For future use Value after reset: 0x0
13	RX_CASC_EN	R/W	Cascode Enable Value after reset: 0x0
12	RSV_12	R/W	For future use Value after reset: 0x0
11	RX_AMP_PT	R/W	Temp Profile Select Value after reset: 0x1
10	RX_VGA_PT	R/W	Temp Profile Select Value after reset: 0x1
9	RX_LNA2_PT	R/W	Temp Profile Select Value after reset: 0x1
8	RX_LNA1_PT	R/W	Temp Profile Select Value after reset: 0x1
7	RX_AMP_EN	R/W	Block Enable Value after reset: 0x0
6	RX_VGA_EN	R/W	Block Enable Value after reset: 0x0
5	RX_LNA2_EN	R/W	Block Enable Value after reset: 0x0
4	RX_LNA1_EN	R/W	Block Enable Value after reset: 0x0
3	RSV_3	R/W	For future use Value after reset: 0x0
2	RSV_2	R/W	For future use Value after reset: 0x0
1	HIGH_LIN_MODE	R/W	High Lineraity Mode Enable (1) Value after reset: 0x0
0	PHASE_OFFSET_EN	R/W	Phase offset Enable Value after reset: 0x0

RXCOM_BIAS1 Register

· Name: RX Common Bias1 Register

· Description:

· Size: 16 bits

· Offset: 0x3C

· Reset: 0x4924

15	14:12	11:9	8:6	5:3	2:0
RSV_15	RX_PS_BIAS	RX_AMP_BIAS	RX_VGA_BIAS	RX_LNA2_BIAS	RX_LNA1_BIAS

Table: RXCOM_BIAS1 Register field descriptions

Bits	Name	Access	Description
15	RSV_15	R/W	For future use Value after reset: 0x0
14:12	RX_PS_BIAS	R/W	For future use Value after reset: 0x4
11:9	RX_AMP_BIAS	R/W	Block bias set Value after reset: 0x4
8:6	RX_VGA_BIAS	R/W	Block bias set Value after reset: 0x4
5:3	RX_LNA2_BIAS	R/W	Block bias set Value after reset: 0x4
2:0	RX_LNA1_BIAS	R/W	Block bias set Value after reset: 0x4

RXCOM_BIAS2 Register

· Name: RX Common Bias2 Register

· Description:

· Size: 16 bits

· Offset: 0x3D

· Reset: 0x0091

15:13	12:10	9:8	7:5	4:2	1:0
RSV_15_13	RSV_12_10	RSV_9_8	RX_AMP_CASC_BIAS	RX_VGA_CASC_BIAS	RX_LNA_CASC_BIAS

Table: RXCOM_BIAS2 Register field descriptions

Bits	Name	Access	Description
15:13	RSV_15_13	R/W	For future use Value after reset: 0x0
12:10	RSV_12_10	R/W	For future use Value after reset: 0x0
9:8	RSV_9_8	R/W	For future use Value after reset: 0x0
7:5	RX_AMP_CASC_BIAS	R/W	For future use Value after reset: 0x4
4:2	RX_VGA_CASC_BIAS	R/W	For future use Value after reset: 0x4
1:0	RX_LNA_CASC_BIAS	R/W	For future use Value after reset: 0x1

TX_RX_SPARE Register

· Name: Spare Register for Channels

· Description:

· Size: 16 bits

· Offset: 0x3E

· Reset: 0x0000

15:8	7	6	5:3	2	1:0
RSV_15_8	PDET_CPL_RX_EN	PDET_CPL_TX_EN	PDET_COM_ATEST_CTRL	PDET_DIFF	PDET_HP_EN

Table: TX_RX_SPARE Register field descriptions

Bits	Name	Access	Description
15:8	RSV_15_8	R/W	RX related spare register Value after reset: 0x0
7	PDET_CPL_RX_EN	R/W	RX Common Pdet coupler EN Value after reset: 0x0
6	PDET_CPL_TX_EN	R/W	TX Common Pdet coupler EN Value after reset: 0x0
5:3	PDET_COM_ATEST_CTRL	R/W	Controls the testing scheme Value after reset: 0x0
2	PDET_DIFF	R/W	PDET Diff enable Value after reset: 0x0
1:0	PDET_HP_EN	R/W	TX related spare register Value after reset: 0x0

ADC_DATA_CHn (for n = 1; n <= 32) Register

· Name: ADC Data Register

· Description: ADC data registers.
ADC outputs from 32 channels - refer to ADC MUX selection (ADC_SEL[4:0]) in ADC_CFG register for correspondence between ADC data registers and channels.

· Size: 16 bits

· Offset: 0x3F + (n-1)*0x1

· Reset: 0x0000

15:11	10	9:0
RSV_15_11	DONE	VALUE

Table: ADC_DATA_CHn (for n = 1; n <= 32) Register field descriptions

Bits	Name	Access	Description
15:11	RSV_15_11	R	For future use Value after reset: 0x0
10	DONE	R	Done signal for ADC Value after reset: 0x0
9:0	VALUE	R	Data Value after reset: 0x0

PA_LNA_DAC_CFG1 Register

· Name: DAC Configuration Register - 1

· Description:

· Size: 16 bits

· Offset: 0x5F

· Reset: 0x037B

15:10	9:0
BUFFER_CONTROL	PA_LNA_CONTROL

Table: PA_LNA_DAC_CFG1 Register field descriptions

Bits	Name	Access	Description
15:10	BUFFER_CONTROL	R/W	[15:13] - For future use. [12:10] - 3-bits buffer stage control bits. Value after reset: 0x0
9:0	PA_LNA_CONTROL	R/W	1-PA, 0 -LNA (DAC_ON Register controls) [9] - DAC @ register 0x6C [8] - DAC @ register 0x6B [7] - DAC @ register 0x6A [6] - DAC @ register 0x69 [5] - DAC @ register 0x68 [4] - DAC @ register 0x67 [3] - DAC @ register 0x66 [2] - DAC @ register 0x65 [1] - DAC @ register 0x64 [0] - DAC @ register 0x63 Value after reset: 0x37B

PA_LNA_DAC_CFG2 Register

· Name: DAC Configuration Register - 2

· Description:

· Size: 16 bits

· Offset: 0x60

· Reset: 0x014A

15:10	9:0
RSV_15_10	V_H_CONTROL

Table: PA_LNA_DAC_CFG2 Register field descriptions

Bits	Name	Access	Description
15:10	RSV_15_10	R/W	For future use Value after reset: 0x0
9:0	V_H_CONTROL	R/W	1-H-Pol, 0 -V-Pol [9] - DAC @ register 0x6C [8] - DAC @ register 0x6B [7] - DAC @ register 0x6A [6] - DAC @ register 0x69 [5] - DAC @ register 0x68 [4] - DAC @ register 0x67 [3] - DAC @ register 0x66 [2] - DAC @ register 0x65 [1] - DAC @ register 0x64 [0] - DAC @ register 0x63 Value after reset: 0x14A

PA_LNA_DAC_CFG3 Register

· Name: DAC Configuration Register - 3

· Description: The PA_LNA_DAC_CFG3 provides an enable bit for each DAC. Writing 1 to an enable bit enables the associated DAC. Writing 0 disables the DAC.
When a LCL_REG_WR or GBL_REG_WR command is issued, the register bits are updated dependent on the setting of the corresponding bits in the PA_LNA_DAC_CFG1 register and the DAC Load bits (TAL, RAL) in byte3 of the command.

· Size: 16 bits

· Offset: 0x61

· Reset: 0x0000

15:14	13	12:10	9	8	7	6	5	4	3	2	1	0
RSV_15_14	RSV_13	RSV_12_10	PA_LNA_EN10	PA_LNA_EN9	PA_LNA_EN8	PA_LNA_EN7	PA_LNA_EN6	PA_LNA_EN5	PA_LNA_EN4	PA_LNA_EN3	PA_LNA_EN2	PA_LNA_EN1

Table: PA_LNA_DAC_CFG3 Register field descriptions

Bits	Name	Access	Description
15:14	RSV_15_14	R/W	For future use Value after reset: 0x0
13	RSV_13	R/W	For future use Value after reset: 0x0
12:10	RSV_12_10	R/W	For future use Value after reset: 0x0
9	PA_LNA_EN10	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x6C Value after reset: 0x0
8	PA_LNA_EN9	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x6B Value after reset: 0x0
7	PA_LNA_EN8	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x6A Value after reset: 0x0
6	PA_LNA_EN7	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x69 Value after reset: 0x0
5	PA_LNA_EN6	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x68 Value after reset: 0x0
4	PA_LNA_EN5	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x67 Value after reset: 0x0
3	PA_LNA_EN4	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x66 Value after reset: 0x0
2	PA_LNA_EN3	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x65 Value after reset: 0x0
1	PA_LNA_EN2	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x64 Value after reset: 0x0
0	PA_LNA_EN1	R/W	1: ON (enable), 0: OFF (disable) - DAC @ register 0x63 Value after reset: 0x0

PA_LNA_DAC_CFG4 Register

· Name: DAC Configuration Register - 4

· Description:

· Size: 16 bits

· Offset: 0x62

· Reset: 0x0000

15:12	11:8	7:4	3:0
LNA_DAC_RES_CONTROL	PA_DAC_RES_CONTROL	LNA_DAC_REF_VOLTAGE	PA_DAC_REF_VOLTAGE

Table: PA_LNA_DAC_CFG4 Register field descriptions

Bits	Name	Access	Description
15:12	LNA_DAC_RES_CONTROL	R/W	4-bits DAC resolution control for LNA DACs Value after reset: 0x0
11:8	PA_DAC_RES_CONTROL	R/W	4-bits DAC resolution control for PA DACs Value after reset: 0x0
7:4	LNA_DAC_REF_VOLTAGE	R/W	4-bits reference setting for LNA DACs Value after reset: 0x0
3:0	PA_DAC_REF_VOLTAGE	R/W	4-bits reference setting for PA DACs Value after reset: 0x0

DAC_ONn (for n = 1; n <= 10) Register

· Name: DAC states for ON mode

· Description: DAC ON-values.

· Size: 16 bits

· Offset: 0x63 + (n-1)*0x1

· Reset: 0x0000

15:9	8:0
RSV_15_9	DAC_FINE_ON_CONT

Table: DAC_ONn (for n = 1; n <= 10) Register field descriptions

Bits	Name	Access	Description
15:9	RSV_15_9	R/W	For future use Value after reset: 0x0
8:0	DAC_FINE_ON_CONT	R/W	9-bit DAC data for ON case Value after reset: 0x0

DAC_PA_OFF Register

· Name: PA DAC states for OFF mode

· Description: PA DAC OFF-values.

· Size: 16 bits

· Offset: 0x6D

· Reset: 0x0000

15:9	8:0
RSV_15_9	DAC_PA_OFF_CONT

Table: DAC_PA_OFF Register field descriptions

Bits	Name	Access	Description
15:9	RSV_15_9	R/W	For future use Value after reset: 0x0
8:0	DAC_PA_OFF_CONT	R/W	9-bit DAC data for OFF case (apply this to DACs set as "PA" by PA_LNA_CONTROL bits @ register 0x5F). Value after reset: 0x0

DAC_LNA_OFF Register

· Name: LNA DAC states for OFF mode

· Description: LNA DAC OFF-values.

· Size: 16 bits

· Offset: 0x6E

· Reset: 0x0000

15:9	8:0
RSV_15_9	DAC_LNA_OFF_CONT

Table: DAC_LNA_OFF Register field descriptions

Bits	Name	Access	Description
15:9	RSV_15_9	R/W	For future use Value after reset: 0x0
8:0	DAC_LNA_OFF_CONT	R/W	9-bit DAC data for OFF case (apply this to DACs set as "LNA" by PA_LNA_CONTROL bits @ register 0x5F). Value after reset: 0x0

DAC_BIAS_CTRL Register

· Name: DAC Bias Control Register

· Description:

· Size: 16 bits

· Offset: 0x6F

· Reset: 0x0000

15:10	9:0
RSV_15_10	DAC_BIAS_CTRL

Table: DAC_BIAS_CTRL Register field descriptions

Bits	Name	Access	Description
15:10	RSV_15_10	R/W	For future use. Value after reset: 0x0
9:0	DAC_BIAS_CTRL	R/W	[9] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x6C [8] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x6B [7] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x6A [6] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x69 [5] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x68 [4] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x67 [3] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x66 [2] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x65 [1] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x64 [0] - 1: ON (enable), 0: OFF (disable) - DAC @ register 0x63 Value after reset: 0x0

DAC_STATUS Register

· Name: DAC Status Register

· Description: Shows the status of the DAC control output signals.

· Size: 16 bits

· Offset: 0x70

· Reset: 0x0000

15	14	13	12	11:10	9:0
TX_DAC_EN	RX_DAC_EN	TAL	RAL	RSV_11_10	DAC_STATE

Table: DAC_STATUS Register field descriptions

Bits	Name	Access	Description
15	TX_DAC_EN	R	TX DAC enable status. When set to 1, all DACs are switched to their respective ON state that are - configured as 'PA' in the PA_LNA_DAC_CFG1 register, and - enabled in the PA_LNA_DAC_CFG3 register. Otherwise, they are switched to the OFF state according to the setting in the PA_DAC_OFF register. Value after reset: 0x0
14	RX_DAC_EN	R	RX DAC enable status. When set to 1, all DACs are switched to their respective ON state that are - configured as 'LNA' in the PA_LNA_DAC_CFG1 register, and - enabled in the PA_LNA_DAC_CFG3 register. Otherwise, they are switched to the OFF state according to the setting in the LNA_DAC_OFF register. Value after reset: 0x0
13	TAL	R	Registered TAL bit status. This bit will be updated according to the TX DAC Load (TAL) bit value in byte3 of a LCL/GBL_FBS command. Value after reset: 0x0
12	RAL	R	Registered RAL bit status. This bit will be updated according to the RX DAC Load (RAL) bit value in byte3 of a LCL/GBL_FBS command. Value after reset: 0x0
11:10	RSV_11_10	R	For future use. Value after reset: 0x0
9:0	DAC_STATE	R	DAC state status. 1: ON (enable), 0: OFF (disable) The DAC assignment is the same as for DAC_BIAS_CTRL[9:0] bit field in DAC_BIAS_CTRL register.0 for OFF state and 1 for ON state Value after reset: 0x0

OTP_CFG Register

· Name: OTP Configuration Register

· Description: This register controls the OTP operations when the oscillator clock is disabled or not running.

· Size: 16 bits

· Offset: 0x71

· Reset: 0x0014

15	14	13	12:10	9:6	5	4	3:2	1	0
OTP_FSM_START	RSV_14	OTP_DIN_LATCH	OTP_WR_BIT	OTP_RW_ADDRESS	OTP_PROG	OTP_POR	OTP_CUR	OTP_READ	OTP_EN

Table: OTP_CFG Register field descriptions

Bits	Name	Access	Description
15	OTP_FSM_START	R	OTP FSM start pin Value after reset: 0x0
14	RSV_14	R/W	Reserved for random r/w by the user. Value after reset: 0x0
13	OTP_DIN_LATCH	W	Latch OTP output data (otp_din[7:0]) to OTP_DATAn (n=1..16) registers. Read and latch at the same time, read is from previously latched data. Value after reset: 0x0
12:10	OTP_WR_BIT	R/W	Bit number to burn during program mode. Note: Fuses can only be burned one at a time. Value after reset: 0x0
9:6	OTP_RW_ADDRESS	R/W	OTP read/write address bank select. Selection of one out of 16 8bit banks for program or for sense. Value after reset: 0x0
5	OTP_PROG	R/W	OTP program mode enable. When this bit is set to 1, fuse i, selected by OTP_WR_BIT of the bank selected by OTP_RW_ADDRESS, will be burned. Value after reset: 0x0
4	OTP_POR	R/W	OTP power-on reset. Only during programming, set OTP_POR to 0. At all other times, Set POR to 1 , for preventing accidental fuse burn. Value after reset: 0x1
3:2	OTP_CUR	R/W	OTP current control. These two bits are used to test the robustness of the read operation. The nominal read operation is done by setting OTP_CUR=0x1. 00: Reduced reference current. 01: Normal operation (default). 10: Enhanced reference current. 11: Extremely enhanced reference current (not in use). Value after reset: 0x1
1	OTP_READ	R/W	OTP read enable. When OTP_READ=1, the 8 fuses of the selected bank are read. Value after reset: 0x0
0	OTP_EN	R/W	OTP enable. Activates the current generation circuit used in read mode. Once activated, the read of fuses is enabled. Value after reset: 0x0

OTP_DATAn (for n = 1; n <= 8) Register

· Name: OTPn Data Register

· Description: OTP data are stored in these registers.

· Size: 16 bits

· Offset: 0x72 + (n-1)*0x1

· Reset: 0x0000

15:8	7:0
OTP_DATA_BYTE1	OTP_DATA_BYTE0

Table: OTP_DATAn (for n = 1; n <= 8) Register field descriptions

Bits	Name	Access	Description
15:8	OTP_DATA_BYTE1	R/W	OTP data (high byte) at address 2^n. Value after reset: 0x0
7:0	OTP_DATA_BYTE0	R/W	OTP data (low byte) at address 2^n. Value after reset: 0x0