Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor 公司 based in Bengaluru, India, specializing in 高-performance chip design for global 5G/6G, defence, satellite communication, and 工业的 物联网 markets. 后退ed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

职位描述

We seek a 高ly skilled and experienced Custom IC Layout Lead to manage multiple analog/mixed-signal IC layout projects and lead a 团队 of junior layout engineers. In this role, you will drive full-chip layout execution across a variety of 应用s and process technologies, while providing technical direction, mentorship, and project oversight. You will collaborate closely with circuit designers, verification 团队s, program management, and packaging engineers to ensure first-pass silicon success in complex technologies.

职责 

• Execute full custom layout of analog/mixed-signal blocks (e.g., ADCs, DACs, PLLs, LDOs, etc.)
• Lead, mentor, and re查看 the work of a 团队 of junior layout engineers, providing technical guidance and quality oversight
• Plan, prioritize, and manage layout execution across multiple concurrent projects, coordinating schedules and resources to meet tapeout deadlines
• Drive layout strategy and technology qualification across multiple process nodes and technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD)
• Collaborate with design engineers to optimize layout for performance, area, and reliability
• Perform layout verification, including DRC, LVS, and parasitic extr行动
• 申请 layout techniques to mitigate issues such as crosstalk, IR drop, and latch-up
• Provide 支持 for post-layout simulations and tapeout activities
• Maintain design 文档 and participate in peer layout re查看s
• Interface with packaging and assembly 团队s to ensure compliance with manufacturing rules
• Work with the design and the foundry 团队 for wafer 步 plan and wafer matrix

要求

• Experience: 12-15 years of hands-on experience in RFIC/MMIC/analog/mixed-signal/custom layout design across multiple process technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD), including experience managing multiple concurrent projects and mentoring junior layout engineers.
• Leadership & Project Management:
  • Pr烤箱 track record managing multiple layout projects simultaneously, from planning through tapeout
  • Experience leading, mentoring, and re查看ing the work of junior layout engineers, including technical training and career development
  • Strong cross-功能al coordination with design, verification, program management, and foundry 团队s to align priorities and schedules
• Technical Expertise:
  • Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers
  • Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus
• Process Knowledge: Pr烤箱 experience working across multiple process technologies, including SiGe, BiCMOS, SOI, and BCD, with the ability to ramp new nodes quickly and guide the 团队 through technology-specific layout considerations
• Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations
• Tools Proficiency:
  • Experienced with Cadence and Calibre tools in a Linux environment
  • Scripting skills in SKILL and Perl are desirable
• Design Awareness: Ability to interpret and implement design constraints into 高-quality, manufacturable layouts
• Cross-Disciplinary Knowledge: Familiarity with 包裹 and assembly rules is a plus
• Soft Skills:
  • Strong problem-solving and debugging skills
  • Effective communication and 团队work
  • Flexible, adaptable, and collaborative working style
  • Pr烤箱 leadership skills, including mentoring, delegating, and providing performance feed后退 to junior engineers
  • Strong organizational skills to manage multiple projects and competing priorities