Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor company based in Bengaluru, India, specializing in high-performance chip design for global 5G/6G, defence, satellite communication, and industrial IoT markets. Backed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

Job Description

We seek a highly skilled and motivated Analog/Custom Layout Engineer to join our team. In this role, you will design and deliver robust analog and mixed-signal IC layouts for a variety of applications. You will collaborate closely with circuit designers, verification teams, and packaging engineers to ensure first-pass silicon success in complex technologies.

Responsibilities 

• Execute full custom layout of analog/mixed-signal blocks (e.g., ADCs, DACs, PLLs, LDOs, etc.)
• Collaborate with design engineers to optimize layout for performance, area, and reliability
• Perform layout verification, including DRC, LVS, and parasitic extraction
• Apply layout techniques to mitigate issues such as crosstalk, IR drop, and latch-up
• Provide support for post-layout simulations and tapeout activities
• Maintain design documentation and participate in peer layout reviews
• Interface with packaging and assembly teams to ensure compliance with manufacturing rules
• Work with the design and the foundry team for wafer step plan and wafer matrix.

Requirements

• Experience: 1-2 years of hands-on experience in analog/custom layout design using CMOS/SiGe processes.
• Technical Expertise:
  • Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers
  • Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus
• Process Knowledge: Familiarity with SiGe, BiCMOS, SOI, and BCD technologies is advantageous
• Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations
• Tools Proficiency:
  • Experienced with Cadence and Calibre tools in a Linux environment
  • Scripting skills in SKILL and Perl are desirable
• Design Awareness: Ability to interpret and implement design constraints into high-quality, manufacturable layouts
• Cross-Disciplinary Knowledge: Familiarity with package and assembly rules is a plus
• Soft Skills:
  • Strong problem-solving and debugging skills
  • Effective communication and teamwork
  • Flexible, adaptable, and collaborative working style