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Senior Staff Digital Design Engineer

Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor company based in Bengaluru, India, specializing in high-performance chip design for global 5G/6G, defence, satellite communication, and industrial IoT markets. Backed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

Job Description

Preferred

  • Knowledge of digital DFT is great plus.
  • Experience with Cadence design tools for synthesis, timing analysis, DFT, and verification is a great plus.
  • Knowledge of UVM methodology for SystemVerilog-based verification.
  • Knowledge of Analog-Mixed Signal simulations on Cadence Virtuoso suite.
  • Knowledge of SRAM BIST and Error Correction Code (ECC) is desired.
  • Bug tracking to ensure a robust solution.
  • Responsibilities 

    • Lead a team of RTL, DV, DFT, and PD engineers and manage them to plan and deliver multiple concurrent projects.
    • Work closely with the RF/analog design leads and marketing/applications teams to understand and create specification documents. Propose resource allocation and timeline for delivery.
    • Propose digital architecture and develop RTL code starting from scratch.
    • Guide junior designers and other digital engineers and help them resolve issues.

    Requirements

    • B.E./B.Tech. with 8+ years or M.S./M.Tech. with 5+ years in digital design.
    • Proven experience taking designs from spec to GDS.
    • Strong leadership and project management skills to guide DFT, verification, and physical design teams.
    • Excellent communication and collaboration with RF/Analog leads for spec development.
    • Deep expertise in digital design flow: RTL, synthesis, constraints, formal verification, DFT, STA, and verification.
    • Proficient in digital concepts: register maps, state machines, CDCs, timing constraints.
    • Familiar with communication protocols (SPI, I2C, I3C) and memory integration (SRAM, EFuse, EEPROM).
    • Working knowledge of physical design, ECOs, DFT, and UVM.
    • Skilled in RTL development and understanding legacy code.
    • Strong documentation, teamwork, and cross-functional collaboration.
    • Self-driven, motivated, and capable of leading multidisciplinary teams.
      Job Title

      Senior Staff Digital Design Engineer

      Department

      Engineering

      Location

      India – Bangalore Design Center