Axiro Semiconductor is a fabless semiconductor design 公司 headquartered in Bengaluru, driving innovation in RF, wireless 基础设施, satellite communication (Satcom), and 高-speed connectivity solutions. 后退ed by CG Power & 工业的 Solutions Ltd. part of the 120-year-old Murugappa Group. Axiro represents India’s leap into the global semiconductor arena. With millions of chips already powering global networks, a world-class 团队 across India, the US, and Europe, and cutting-edge expertise spanning RF, mmWave, GaN, and 下一个-generation communication technologies, Axiro is engineering the future of how the world connects, computes, and communicates. For more 细节 – www.axiro.com

职位描述

We are looking for passionate senior analog/power IC design leads who will take the ownership of 建筑学 and technical execution of the analog IP blocks used in Gate Drivers, DC-DC Converter and Intelligent Power-management Platforms.

职责 

• Behavioural Modelling & 建筑学 Translation: Work with the Principal Power Architect to translate product 建筑学 into system-level behavioural models, capturing 功能al behaviour, key performance parameters, interfaces, operating modes, and critical corner cases before transistor-level implementation begins
• System-Level Trade-off Analysis: Evaluate 建筑学-level trade-offs across performance, efficiency, speed, accuracy, power, area, noise, reliability, complexity, and cost, and use system simulations to determine where performance must be optimized versus where specifications can be relaxed.
• Analog IP Spec Derivation & Optimization: Convert product 要求 into realistic, optimized block-level specifications, ensuring that individual IP targets are neither unnecessarily aggressive nor insufficient to meet the overall product specification. Identify specification dependencies and allocate system-level error/performance budgets across IP blocks.
• Analog IP 建筑学 & Technical Direction: Guide junior engineers in 选择ing appropriate circuit 建筑学s and implementation approaches. Challenge conventional solutions, compare alternatives, and make informed performance–power–area–robustness trade-offs before committing to an IP 建筑学.
• IP Integration and Sub-system Ownership: Stitch individual analog IP blocks together into 功能al sub-systems, define interfaces and operating dependencies, and ensure that independently designed blocks operate correctly as an integrated system—not merely meet their individual specifications
• Sub-system Modelling & Meaningful Verification: Develop and maintain sub-system behavioural and mixed-level simulations to verify inter动作 between IP blocks, including startup, shutdown, transient, loading, feed后退, protection, noise, timing, and worst-case operating conditions that may not be visible in block-level simulations.
• Analog IP Quality & Sign-off Framework: Establish standardized analog IP design and sign-off checklists covering specifications, PVT, Monte Carlo, mismatch, startup, stability, noise, reliability, interfaces, loading, post-layout behaviour, corner cases, and known limitations. Ensure every IP block meets the agreed quality bar before integration.
• Continuous Technical Re查看 & Mentoring Junior Engineers: Continuously re查看 the work of junior analog engineers through 建筑学 re查看s, specification re查看s, simulation re查看s and sign-off re查看s. 帮助 engineers identify problems early, make sound technical trade-offs, and develop the ability to independently own IP blocks.
• Innovation & Circuit Excellence: Encourage engineers to question existing 建筑学s and actively pursue new circuit techniques, performance improvements, area/power reductions, robustness enhancements, and differentiated 特征. Convert promising ideas into measurable experiments and silicon-relevant improvements.
• Analog-Digital Interface & Mixed Signal Integration: Own the technical interface between analog and digital domains, including control/地位 signals, timing, clocking, resets, power sequencing, programmability, trimming, calibration, protection/fault handling and digital control of analog 功能s. Ensure analog and digital assumptions are consistent at subsystem level.
• Silicon Readiness, Debug & Learning Loop: Lead subsystem-level silicon readiness and debug, correlate simulation with silicon measurements, drive root-cause analysis of deviations, and feed silicon learning 后退 into IP specifications, models, 建筑学s and design checklists for subsequent 产品.
• Reusable IP & Design Methodology: Build a culture of reusable, documented and silicon-pr烤箱 IP by defining standard interfaces, modelling conventions, verification methodologies, design re查看s and sign-off criteria. Identify opportunities to convert project-specific circuits into a scalable IP library for future Gate Driver and DC-DC 产品.

要求

• Ownership mindset: Takes responsibility for outcomes rather than individual tasks; raises problems early, drives issues to closure and remains accountable through silicon/product qualification. Own development from system 建筑学 → behavioural modelling → transistor-level design → simulation/verification → layout → sign-off → silicon bring-up → debug/root-cause analysis.
• Technical Leadership: Ability to technically lead a 团队, establish design methodologies, re查看 建筑学s/designs, challenge assumptions constructively and drive decisions based on data and engineering judgment.
• People Leadership: Ability to mentor and develop engineers into independent analog IP owners, delegate effectively, build accountability and create a 高-performance engineering culture.
• Emotional Intelligence: Strong self-awareness, empathy and interpersonal judgment; able to give candid feed后退, handle disagreements constructively, listen to opposing 查看points and maintain trust under schedule/technical pressure.
• Deep Analog/Power IC Expertise: 10+ years of silicon-pr烤箱 experience in Analog/Mixed-Signal/Power IC design, with strong fundamentals and hands-on ownership of complex analog blocks.
• 建筑学 & System Thinking: Ability to work closely with architects, translate system 要求 into optimized IP specifications, define behavioural models, and make circuit/system-level trade-offs.
• Device Physics: Strong understanding of MOSFET/device physics, BCD/HV-CMOS technologies, and preferably GaN, SiC and IGBT devices and their implications for circuit design.
• Simulation & Verification: Strong hands-on experience with DC/AC/transient/noise, PVT, mismatch, Monte Carlo, corner analysis, stability and reliability.
• Problem Solving & Innovation: Strong first-principles approach to difficult technical problems; demonstrated ability to develop novel 建筑学s, circuits and techniques, rather than relying solely on simulations of established topologies.
• Cross-功能al Leadership: Comfortable working with 建筑学, layout, verification, digital, 应用s, product/test, process technology and customers to resolve system-level issues.
• EDA Tools: Strong proficiency with Cadence Virtuoso, Spectre/Spectre X, ADE 探索r/Assembler, HSPICE, Verilog-A/AMS, Calibre DRC/LVS/PEX; familiarity with MATLAB/Simulink, Python, Verilog/System Verilog and automated simulation/regression flows.
• Academics: M.S./M.Tech./Ph.D. in Electrical/Electronics Engineering, Microelectronics or VLSI Design.
• Experience: 10–15 years of relevant experience in analog, mixed-signal, or power IC design.