职位描述

We are seeking an experienced ASIC RTL Design Engineer Engineer to of 高-performance RF and mixed-signal ICs. This role requires strong in ASIC and RTL

职责 

• Lead a 团队 of RTL, DV, DFT, and PD engineers and manage them to plan and deliver multiple concurrent projects.
• Work closely with the RF/analog design leads and marketing/应用s 团队s to understand and create specification documents. Propose resource al地点 and timeline for delivery.
• Propose digital 建筑学 and develop RTL code starting from scratch.
• Guide junior designers and 其他 digital engineers and 帮助 them resolve issues.

要求

• B.E./B.Tech. with 8+ years or M.S./M.Tech. with 5+ years in digital design.
• Pr烤箱 experience taking designs from spec to GDS.
• Strong leadership and project management skills to guide DFT, verification, and physical design 团队s.
• Excellent communication and collaboration with RF/Analog leads for spec development.
• Deep expertise in digital design flow: RTL, synthesis, constraints, formal verification, DFT, STA, and verification.
• Proficient in digital concepts: register maps, 状态 machines, CDCs, timing constraints.
• Familiar with communication protocols (SPI, I2C, I3C) and memory integration (SRAM, EFuse, EEPROM).
• Working knowledge of physical design, ECOs, DFT, and UVM.
• Skilled in RTL development and understanding legacy code.
• Strong 文档, 团队work, and cross-功能al collaboration.
• Self-driven, motivated, and capable of leading multidisciplinary 团队s.

 

Preferred

• Knowledge of digital DFT is great plus.
• Experience with Cadence design tools for synthesis, timing analysis, DFT, and verification is a great plus.
• Knowledge of UVM methodology for SystemVerilog-based verification.
• Knowledge of Analog-Mixed Signal simulations on Cadence Virtuoso suite.
• Knowledge of SRAM BIST and Error Correction Code (ECC) is desired.