Axiro Semiconductor is a fabless semiconductor design 公司 headquartered in Bengaluru, driving innovation in RF, wireless 基础设施, satellite communication (Satcom), and 高-speed connectivity solutions. 后退ed by CG Power & 工业的 Solutions Ltd. part of the 120-year-old Murugappa Group. Axiro represents India’s leap into the global semiconductor arena. With millions of chips already powering global networks, a world-class 团队 across India, the US, and Europe, and cutting-edge expertise spanning RF, mmWave, GaN, and 下一个-generation communication technologies, Axiro is engineering the future of how the world connects, computes, and communicates. For more 细节 – www.axiro.com

职位描述

The IC Packaging and RF Simulation Intern will 支持 the design, modeling, and optimization of advanced semiconductor 包裹s and RF interconnect structures. The intern will work closely with 包裹 Design, Signal Integrity (SI), Power Integrity (PI), and RF Engineering 团队s to analyze electrical performance, perform electromagnetic simulations, and contribute to the development of 下一个-generation semiconductor 产品.

职责 

• Perform electromagnetic (EM), RF, and signal integrity simulations for IC 包裹s, substrates, and 高-speed interconnects.
• Develop and vali日期 simulation models using tools such as Ansys HFSS, CST Studio Suite, ADS, and SIwave.
• Analyze S-parameters, insertion loss, return loss, impedance discontinuities, crosstalk, and resonance effects.
• 支持 包裹 design optimization to meet electrical and RF performance 要求.
• Correlate simulation results with laboratory measurements and characterization data.
• Assist in 包裹 electrical model generation and validation.
• Prepare technical reports, presentations, and engineering 文档.
• Collaborate with Packaging, Design, Validation, and Manufacturing 团队s.

要求

• Pursuing or recently completed a B.E./B.Tech/M.E./M.Tech in Electronics & Communication, Electrical, Communication, RF & Microwave Engineering, Semiconductor Technology, or related fields.
• Basic understanding of Electromagnetic Theory, RF & Microwave Fundamentals, 变速器 Lines, Signal Integrity (SI), Power Integrity (PI), and Semiconductor Packaging Concepts.

Preferred Skills

• Familiar with Ansys HFSS, CST Microwave Studio, Keysight ADS, Ansys SIwave, or Cadence AWR.
• Exposure Wire Bond, Flip-Chip BGA, FC-CSP, WLCSP, or 2.5D/3D packaging.
• Programming or scripting knowledge in Python, MATLAB, or VBA.
• Understanding 包裹 substrates, PCB design, and 高-speed interfaces.

Learning Opportunities

• Hands-on experience with semiconductor 包裹 design and RF simulation.
• Exposure advanced 包裹 technologies and 高-speed interconnect design.
• Experience correlating simulation and measurement data.
• Mentorship from experienced 包裹, SI/PI, and RF engineers.

Desired Attributes

• Strong analytical and problem-solving skills.
• Effective communication and presentation abilities.
• Ability to work in a collaborative engineering environment.
• Passion for RF engineering, semiconductor packaging, and simulation technologies.

Preferred CGPA: 7.0/10 or above