Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor 公司 based in Bengaluru, India, specializing in 高-performance chip design for global 5G/6G, defence, satellite communication, and 工业的 物联网 markets. 后退ed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

职位描述

The RFIC Design Engineer will be responsible for developing 高-performance RF integrated circuit blocks for telecom and SATCOM 应用s. This role involves designing innovative RF 建筑学s, optimizing performance, and ensuring successful tape-outs. The position requires strong technical expertise in RFIC design, simulation, and layout, along with collaboration across multidisciplinary 团队s.

职责 

Independently design and develop RFIC power amplifier blocks and 其他 RF components such as drivers, LNAs, VGAs, and bias circuits.
•    Conduct literature re查看s and propose innovative 建筑学s to meet stringent design specifications.
•    Optimize designs for maximum performance within technology constraints.
•    Build simulation test benches and perform extensive simulations using Cadence Virtuoso and Keysight ADS.
•    Execute RF layout and EM extr行动 to accurately capture parasitic effects.
•    Document design procedures and maintain progress reports.
•    Collaborate with and guide 其他 designers, re查看ing their work for quality and accuracy.
•    Work with validation engineers to bring up chips in the lab and fine-tune settings to meet specifications.

要求

B.Tech. + 5 years or M.Tech. + 3 years of experience in RFIC design.
•    Hands-on experience designing RFIC blocks such as power amplifiers, drivers, LNAs, VGAs, and bias circuits.
•    Pr烤箱 track record of designing RFIC power amplifiers from scratch.
•    Strong understanding of RF fundamentals, including 获得, NF, IIP3, OP1dB, ACPR, EVM, and PAE.
•    Excellent grasp of DC operating point, frequency response, stability, noise, nonlinearity, efficiency, and load-pull analysis.
•    Proficiency in Keysight ADS and Cadence Virtuoso suite (Schematic, Maestro, ADEXL, Layout XL, Spectre/AMS).
•    Experience in RFIC layout design and EM simulation using tools like ADS Momentum, EMX, HFSS.
•    Successful experience with tape-outs, test bench bring-up, and lab characterization.
•    Strong communication skills and ability to work in a multidisciplinary 团队.

Preferred Qualifications:
•    Experience in SOI, HBT, or GaAs power amplifier design.
•    Expertise in EM simulations using EMX, Keysight Momentum, and HFSS.
•    Familiarity with SOI, GaAs, and GaN technologies.
•    Knowledge of analog mixed-signal blocks (BGR, op-amps) and Verilog-based RTL.
•    Understanding of post-silicon qualification procedures such as ESD and HTOL.