Axiro Semiconductor Pvt. Ltd. is a leading Fabless Semiconductor 公司 based in Bengaluru, India, specializing in 高-performance chip design for global 5G/6G, defence, satellite communication, and 工业的 物联网 markets. 后退ed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

职位描述

The Mixed-Signal Design Engineer will lead the development of advanced analog and mixed-signal IPs for semiconductor 产品 in telecom and SATCOM 应用s. This role involves taking designs from concept to production, ensuring robust 建筑学, performance optimization, and successful tape-outs. The position requires strong technical expertise, leadership skills, and collaboration across multidisciplinary 团队s.

职责 

Drive projects from concept to completion, including specification analysis, 建筑学 definition, and innovative design solutions.
Design and verify mixed-signal circuits such as Sigma-Delta ADCs/DACs, LDOs, temperature sensors, and precision analog blocks.
Develop and guide custom layout strategies for optimal performance.
Collaborate with digital design 团队s to define AMS control specifications.
Conduct weekly 团队 meetings, monitor progress, and ensure timely deliverables.
Train and mentor junior designers to build resilient IPs.
Document design procedures and maintain progress reports.
支持 post-silicon bring-up, characterization, and product release activities.

要求

B.E. + 10 years or M.Tech + 8 years of experience in mixed-signal circuit design using CMOS technologies.
Hands-on experience with low-noise Sigma-Delta converters, LDOs, temperature sensors, and precision analog circuits.
Strong knowledge of op-amps, bandgap references, and biasing circuits from scratch.
Pr烤箱 track record of IP development and problem-solving in design and characterization.
Expertise in Cadence Virtuoso suite (Schematic, Maestro, ADEXL, Layout XL, Spectre/AMS).
Solid understanding of DC operating point, AC simulations, frequency response, stability, noise, INL/DNL, THD, and mismatch analysis.
Experience in taking 产品 from concept to tape-out and production release.
Ability to lead small design 团队s and work in agile, multidisciplinary environments.
Excellent communication and 团队work skills.

Preferred Qualifications:
Strong experience in Sigma-Delta ADC design.
Exposure to 高-precision ICs and 高-voltage (~10V) design.
Working knowledge of digital concepts, SPI/I2C interfaces, AMS simulation, and Verilog RTL.
Familiarity with post-silicon qualification procedures (ESD, HTOL, etc.).