Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor 公司 based in Bengaluru, India, specializing in 高-performance chip design for global 5G/6G, defence, satellite communication, and 工业的 物联网 markets. 后退ed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

职位描述

We are seeking an experienced SoC Design Manager to lead the design and integration of complex System-on-Chip (SoC) solutions for 下一个-generation semiconductor 产品.

In this role, you will manage a 团队 responsible for RTL development, integration, synthesis, timing closure, and physical implementation, ensuring 高-quality execution from concept through tape-out. You will play a critical role in delivering innovative, 高-performance SoCs that meet stringent power, performance, and area 要求.​

This position requires deep expertise in SoC design flows, verification methodologies, and strong leadership skills to drive technical execution and 团队 development.​

职责 

Manage and mentor a 团队 of SoC design engineers, fostering technical excellence and professional growth.​

Oversee RTL design, integration, synthesis, timing analysis, and physical design activities to ensure successful tape-out.​

Define and implement best practices for SoC design flows, verification strategies, and sign-off processes.​

Work closely with 建筑学, IP, verification, physical design, and software 团队s to ensure seamless integration.​

Develop schedules, track progress, and ensure timely delivery of design milestones.​

Evaluate and adopt EDA tools and technologies to improve efficiency and quality.​

Identify design risks early and drive mitigation plans.​

支持 technical discussions with customers as needed for design-related topics.​

要求

Bachelor’s degree in Electrical Engineering or related field; Master’s degree preferred.​

12+ years in semiconductor design, with at least 3–5 years in a leadership or management role.​

Strong understanding of SoC design flows, RTL development, synthesis, timing closure, and physical implementation.​

Familiarity with simulation, formal verification, and DFT methodologies.​

Ability to lead and develop 高-performing 团队s.​

Excellent verbal and written communication skills for internal and external stakeholders.​

Strong analytical skills and ability to resolve complex design challenges.​